Shift register and electronic apparatus

ABSTRACT

Each of stages RS( 1 ), RS( 2 ), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs  1  to  6  is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Applications No. 2000-162671, filed May 31,2000; No. 2000-169002, filed Jun. 6, 2000; and No. 2001-128909, filedApr. 26, 2001, the entire contents of all of which are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a shift register and an electronicapparatus such as a display unit or an imaging apparatus, using thisshift register as a driver.

In an active matrix type liquid crystal display such as a TFT liquidcrystal display, each one line of display pixels arranged in the matrixform is selected, and display data is written in a pixel capacitance ofthe selected pixels, thereby obtaining desired display.

In the TFT liquid crystal display, there are used a gate driver forserially outputting a gate signal for pixel selection to a gate of theTFT functioning as a pixel switching device, and a drain driver foroutputting a drain signal which serves as image data during a gateselection period in parallel. Since the drain driver which outputs usualmoving image data must be constituted by multiple complex transistorsand driven at a high speed, there is adopted a driver consisting ofmonocrystal silicon or polysilicon which can reduce the size of thetransistors and has the high mobility.

On the other hand, since the structure of the gate driver is not verycomplicated as the drain electrode and the gate driver has a low drivingfrequency, it can be theoretically driven by a driver consisting ofamorphous silicon TFTs but it has not been put into practical use.

Among the gate drivers constituted by multiple amorphous silicon TFTs,there are drivers having a threshold value characteristic of each TFTbeing shifted with a lapse of time, or those disadvantageously causingan erroneous operation in the high-temperature environment.

BRIEF SUMMARY OF THE INVENTION

It is an object of the present invention to provide a shift registerwhich can obtain a correct circuit operation even at a high temperatureand obtain a stable operation in a long period of time.

According to a first aspect of the present invention there is provided ashift register,

-   -   each stage of the shift register comprising:    -   a first transistor which has a first control terminal, is turned        on by a signal on a predetermined level supplied from one stage        to the first control terminal, and outputs the signal on a        predetermined level from one end of a first electric current        path to the other end of the first electric current path;    -   a second transistor which has a second control terminal, is        turned on in accordance with a voltage applied to a wiring        between the second control terminal and the other end of the        first electric current path of the first transistor, and outputs        a first or second signal supplied from outside to one end of a        second electric current path as an output signal from the other        end of the second electric current path;    -   a load for outputting a power supply voltage supplied from        outside;    -   a third transistor which has a third control terminal, is turned        on in accordance with a voltage applied to a wiring between the        third control terminal and the other end of the first electric        current path of the first transistor, and outputs the power        supply voltage supplied from the outside through the load from        one end of a third electric current path to the other end of the        third electric current path so that the power supply voltage        outputted from the load is displaced to a voltage on a        predetermined level; and    -   a fourth transistor which has a fourth control terminal, is        turned on in accordance with a voltage applied to a wiring        between the fourth control terminal and the load, and outputs a        reference voltage to one end of a fourth electric current path        from the other end of the fourth electric current path, one end        of the fourth electric current path being connected to the other        end of the second electric current path of the second        transistor,    -   a value (a channel-width/a channel-length of the fourth        transistor) being equal to or larger than another value (a        channel width of the second transistor/s channel length of the        second transistor).

According to a second aspect of the present invention, there is provideda shift register

-   -   each stage of the shift register comprising:    -   a first transistor which has a first control terminal, is turned        on by a signal on a predetermined level supplied from one stage        to the first control terminal, and outputs the signal on a        predetermined level from one end of a first electric current        path to the other end of the first electric current path;    -   a second transistor which has a second control terminal, is        turned on in accordance with a voltage applied to a wiring        between the second control terminal and the other end of the        first electric current path of the first transistor, and outputs        a first or second signal supplied from outside to one end of a        second electric current path as an output signal from the other        end of the second electric current path;    -   a third transistor which has a third control terminal and        outputs a power supply voltage from one end of a third electric        current path to the other end of the third electric current        path;    -   a fourth transistor which has a fourth control terminal, is        turned on in accordance with a voltage applied to a wiring        between the fourth control terminal and the other end of the        first electric current path of the first transistor, and outputs        from one end of a fourth electric current to the other end of        the fourth electric current path the power supply voltage        supplied from the third transistor so that the power supply        voltage outputted from the third transistor is displaced to a        voltage on a predetermined level;    -   a fifth transistor which has a fifth control terminal, is turned        on in accordance with a voltage applied to a wiring between the        fifth control terminal and the third transistor, and outputs a        reference voltage to one end of a fifth electric current path        from the other end of the fifth electric current path, one end        of the fifth electric current path being connected to the other        end of the second electric current path of the second        transistor; and    -   a sixth transistor which has a sixth control terminal and resets        a voltage applied to the wiring between the second control        terminal of the second transistor and the first electric current        path of the first transistor when turned on by turning on the        sixth control terminal by an output signal of the other stage,    -   a value (a channel-width/a channel-length of the fifth        transistor) being larger than another value (a channel-width/a        channel-length of the first transistor).

According to a third aspect of the present invention, there is provideda shift register,

-   -   each stage of the shift register comprising:    -   a first transistor having a control terminal to which an output        signal of a stage on one side is supplied and one end of an        electric current path to which a first voltage signal is        supplied;    -   a second transistor having a control terminal to which an output        signal of a stage on the other side is supplied and one end of        an electric current path to which a second voltage signal is        supplied; and    -   a third transistor which has a control terminal being connected        to the other end of each electric current path of the first and        second transistors, is turned on or off by the first or second        voltage signal supplied to a wiring between the control terminal        and the other end of each electric current path through the        first or second transistor, and outputs from the other end of        the electric current path a first or second clock signal        supplied to one end of the electric current path as an output        signal of that stage when turned on,    -   at least one of the first and second transistor being        constituted so as to be capable of discharging electric charge        accumulated in the wiring by an output signal of the stage on        one side or the other side supplied to the control terminal.

According to a forth aspect of the present invention, there is providedan electronic apparatus comprising:

-   -   (A) a shift register including on each stage:    -   a first transistor which has a first control terminal, is turned        on by a signal on a predetermined level supplied from one stage        to the first control terminal, and outputs the signal on a        predetermined level from one end of a first electric current        path to the other end of the first electric current path;    -   a second transistor which has a second control terminal, is        turned on in accordance with a voltage applied to a wiring        between the second control terminal and the other end of the        first electric current path of the first transistor, and outputs        a first or second signal supplied from outside to one end of a        second electric current path as an output signal from the other        end of the second electric current path;    -   a third transistor which has a third control terminal and        outputs a power supply voltage from one end of a third electric        current path to the other end of the third electric current        path;    -   a fourth transistor which has a fourth control terminal, is        turned on in accordance with a voltage applied to a wiring        between the fourth control terminal and the other end of the        first electric current path of the first transistor, and outputs        from one end of a fourth electric current to the other end of        the fourth electric current path the power supply voltage        supplied from the third transistor so that the power supply        voltage outputted from the third transistor is displaced to a        voltage on a predetermined level;    -   a fifth transistor which has a fifth control terminal, is turned        on in accordance with a voltage applied to a wiring between the        fifth control terminal and the third transistor, and outputs a        reference voltage to one end of a fifth electric current path        from the other end of the fifth electric current path, one end        of the fifth electric current path being connected to the other        end of the second electric current path of the second        transistor; and    -   a sixth transistor which has a sixth control terminal and resets        a voltage applied to the wiring between the second control        terminal of the second transistor and the first electric current        path of the first transistor by turning on the sixth control        terminal by an output signal of the other stage; and    -   (B) a drive device driven in accordance with the output signal        from the second transistor of the shift register,    -   a value (a channel-width/a channel-length of the fifth        transistor) being larger than another value (a channel-width/a        channel-length of the first transistor).

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIG. 1 is a perspective view showing an external appearance structure ofa digital still camera according to a first embodiment of the presentinvention;

FIG. 2 is a circuit diagram of the digital still camera illustrated inFIG. 1;

FIG. 3 is a block diagram showing a circuit structure of a displayportion illustrated in FIG. 2;

FIG. 4 is a view showing a circuit structure of a shift register used asa gate driver;

FIG. 5 is an enlarged view showing the structure of each stage of theshift register illustrated in FIG. 4;

FIG. 6 is a plane view of a TFT constituting the shift register;

FIG. 7 is a cross-sectional view taken along the line VII—VII of the TFTillustrated in FIG. 6;

FIG. 8 is a timing chart showing the operation of the shift registerillustrated in FIG. 4;

FIG. 9 is a view showing the circuit structure of another shiftregister;

FIG. 10 is a block diagram showing the circuit structure of aphotosensor constructed by a double gate transistor;

FIG. 11 is a view showing the circuit structure of a shift register usedas a gate driver depicted in FIG. 3;

FIG. 12 is a timing chart showing the operation of the shift registerillustrated in FIG. 11;

FIG. 13 is a view showing another circuit structure of the shiftregister used as the gate driver depicted in FIG. 3;

FIG. 14 is a timing chart showing the operation of the shift registerillustrated in FIG. 13;

FIG. 15 is a view showing still another circuit structure of the shiftregister used as the gate driver depicted in FIG. 3;

FIG. 16 is a timing chart showing the operation of the shift registerillustrated in FIG. 15;

FIG. 17 is another timing chart showing the operation of the shiftregister illustrated in FIG. 15;

FIG. 18 is a view showing yet another circuit structure of the shiftregister used as the gate driver depicted in FIG. 3;

FIG. 19 is a timing chart showing the operation of the shift registerillustrated in FIG. 18;

FIG. 20 is a view showing the circuit structure of a shift register usedas a gate driver illustrated in FIG. 3 in a second embodiment accordingto the present invention;

FIG. 21 is a timing chart showing a forward operation of the shiftregister illustrated in FIG. 20;

FIG. 22 is a timing chart showing a backward operation of the shiftregister illustrated in FIG. 20;

FIG. 23A is a view showing a forward imaging state of the digital stillcamera in the second embodiment according to the present invention andFIG. 23B is a view showing a displaying state of a display portion;

FIG. 24A is a view showing a backward imaging state of the digital stillcamera in the second embodiment according to the present invention andFIG. 24B is a view showing a displaying state of the display portion;

FIG. 25 is another timing chart showing the forward operation of theshift register illustrated in FIG. 20;

FIG. 26 is another timing chart showing the backward operation of theshift register illustrated in FIG. 20;

FIG. 27 is a view showing a further circuit structure of the shiftregister in the second embodiment according to the present invention;

FIG. 28 is a timing chart showing a forward operation of the shiftregister depicted in FIG. 27;

FIG. 29 is a timing chart showing a backward operation of the shiftregister depicted in FIG. 27;

FIG. 30 is a view showing a still further circuit structure of the shiftregister in the second embodiment according to the present invention;

FIG. 31 is a timing chart showing the forward operation of the shiftregister illustrated in FIG. 27; and

FIG. 32 is a timing chart showing the backward operation of the shiftregister illustrated in FIG. 27.

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

Preferred embodiments according to the present invention will now bedescribed with reference to the accompanying drawings. FIG. 1 is a viewshowing an external appearance structure of a digital still cameraaccording to this embodiment. As shown in the figure, this digital stillcamera is constituted by a camera main body portion 201 and a lens unitportion 202.

The camera main body portion 201 includes a display portion 210 and amode setting key 212a in the front part thereof. The mode setting key212a is a key used for switching between a recording mode for picking upan image and recording it in a later-described memory and a reproductionmode for reproducing the recorded image. The display portion 210 isconstituted by a liquid crystal display. This portion functions as aview finder for displaying an image captured by a lens 202a before imagepickup in the recording mode (monitoring mode) and functions as adisplay for displaying a recorded image in the reproduction mode. Theconfiguration of the display portion 210 will be described later indetail.

The camera main body portion 201 includes on the top face thereof apower supply key 211, a shutter key 212b, a “+” key 212c,a “−” key 212d,and a serial input/output terminal 213. The power supply key 211 is usedfor turning on/off the power supply of the digital still cameral byperforming the slide operation. The shutter key 212b, the “+” key 212cand the “−” key 212d constitute the key input portion 212 together withthe above-described mode setting key 212a.

The shutter key 212b is used for instructing recording of an image inthe recording mode and instructing determination of a selection contentin the reproduction mode. The “+” key 212c and the “−” key 212d are usedto select image data to be displayed on the display portion 210 fromimage data recorded in the image memory in the recording mode or to setconditions at the time of recording/reproduction. The serialinput/output terminal 213 is a terminal to which a cable is inserted inorder to transmit/receive data with respect to an external device (suchas a personal computer or a printer).

The lens unit portion 202 includes the lens 202a for forming an image tobe picked up on a rear surface side of the drawing. The lens unitportion 202 is attached so as to be capable of swiveling 360 degreesaround a shaft joined to the camera main body portion 201 in thevertical direction.

FIG. 2 is a block diagram showing a circuit structure of the digitalstill camera according to this embodiment. As shown in the figure, thisdigital still camera includes: a CCD (Charge Coupled Device) imagingdevice 220; an A/D (Analogue/Digital) converter 221; a CPU (CentralProcessing Unit) 222; a ROM (Read Only Memory) 223; a RAM (Random AccessMemory) 224; a compression/extension circuit 225; an image memory 226;the above-described display portion 210; the key input portion 212; andthe serial input/output terminal 213. These members are connected toeach other through a bus 230. The CCD imaging device 220 and the A/Dconverter 221 are also connected to each other through a dedicated line.An angle sensor 240 indicated by a broken line is not included in thisembodiment (see the later-described second embodiment).

The CCD imaging device 220 has a plurality of imaging pixels formed inthe matrix and photoelectrically converts a light ray image-formed bythe imaging lens 202a to output an electric signal according to theintensity of the light of each pixel. The A/D converter 221 converts ananalog electric signal outputted from the CCD imaging device 220 into adigital signal to be outputted. The CPU 222 controls a circuit in eachportion of the digital still camera by executing a program stored in theROM 223 in accordance with an input from the key input portion 212. TheROM 223 stores a program executed by the CPU 222 as well as fixed data.The RAM 224 is used as a work area when executing a program by the CPU222. In RAM 224 is provided a VRAM area for developing image data to bedisplayed on the display portion 210. The compression/extension circuit225 compresses image data picked-up by the CCD imaging device when theshutter key 212 is operated and converted into a digital signal by theA/D converter 221, and records this image data in the image memory 226.The compression/extension circuit 225 extends image data compressed andrecorded in the image memory 226 when a command for displaying thepicked-up image is issued from the key input portion 212. The imagememory 226 is constituted by a non-volatile storage medium such as aflash memory from which data can not be erased, and records image datapicked-up and compressed as described above. The image memory 226 may beconstituted so as to be detachable from the digital still camera.

FIG. 3 is a block diagram showing the structure of a liquid crystaldisplay constituting the display portion 210. AS shown in the figure,the liquid crystal display has a controller 150, a display area 151, agate driver 152, and a drain driver 153. From the controller 150, acontrol signal group Gcnt is supplied to the gate driver 152, meanwhilea control signal group Dcnt and display data data are supplied to thedrain driver 153.

The controller 150 generates control signal groups Gcnt and Dcnt inaccordance with a control signal from the CPU 222 and supplies them tothe gate driver 152 and the drain driver, respectively. Further, thecontroller 150 reads image data developed in the VRAM area in the RAM224 and supplies it to the drain driver 153 as display data (data) inaccordance with a control signal from the CPU 222.

The display area 151 is constituted by sealing liquid crystal in a pairof substrates, and a plurality of TFTs 161 for active drive are formedin the matrix on one substrate 19 with a-Si layer being used for asemiconductor layer. In each TFT 161, a gate is connected to a gate lineGL, a drain is connected to a drain line DL, and a source is similarlyconnected to each of pixel electrodes formed in the matrix. A commonelectrode to which a predetermined voltage Vcom is applied is formed onthe other substrate, and the common electrode, each pixel electrode andthe liquid crystal therebetween form a pixel capacitance 162. When thealignment state of the liquid crystal varies by electric chargeaccumulated in the pixel capacitance 162, the display area 151 controlsa quantity of light to be transmitted and then displays an image.

The gate driver 152 is constituted by a shift register which operates inaccordance with a control signal group Gcnt from the controller 150. Thegate driver 152 sequentially selects the gate line GL to output apredetermined voltage in accordance with the control signal group Gcntfrom the controller 150. The shift register constituting the gate driver152 will be described later in detail.

The drain driver 153 sequentially fetches display data (data) from thecontroller 150 in accordance with the control signal group Dcnt from thecontroller. When display data (data) corresponding to one line isaccumulated, the drain driver 153 outputs this data to the drain line DLin accordance with the control signal group Dcnt from the controller150, and accumulates it in the pixel capacitance 162 through the TFT 161(ON state) connected to the gate line GL selected by the gate driver152.

The gate driver 152 illustrated in FIG. 3 will now be described indetail. FIG. 4 is a circuit diagram showing the entire structure of thegate driver 152. Assuming that a number of stages of the gate driver 152arranged in the imaging device (a number of the gate lines GL) is n, thegate driver 152 is constituted by n stages RS(1) to RS(n) for outputtinggate signals, a dummy stage RS(n+1) and a dummy stage RS(n+2) forcontrolling the stage RS(n) and the like. FIG. 4 shows the structure inwhich n is an even number not less than 2.

As a control signal Gcnt from the controller, a signal CK1 is suppliedto the odd-numbered stages RS(1), RS(3), . . . , RS(2t−1). A signal CK2is supplied to the even-numbered stages RS(2), RS(4), . . . , RS(2t). Aconstant voltage Vss is supplied from the controller to each stage. Thehigh level of the signals CK1 and CK2 corresponds to +15 (V) and the lowlevel of the same corresponds to −15 (V). Furthermore, the level of theconstant voltage Vss corresponds to −15 (V).

To the first stage RS(1) is supplied a start signal Dst from thecontroller. The high level and the low level of the start signal Dstcorresponds to +15 (V) and −15 (V), respectively. Output signals OUT1 toOUTn−1 are supplied from the respective preceding stages RS(1) toRS(n−1) to the second and the subsequent stages RS(2) to RS(n).Moreover, to each stage RS(k) (k: an arbitrary integer from 1 to n) issupplied an output signal OUTk+1 (however, a reset signal Dend in caseof the last stage RS(n)) from the following stage RS(k+1) as a resetpulse. The output signals OUT1 to OUTn of the respective stages RS(1) toRS(n) are outputted to a plurality of gate lines GL of the imagingdevice 1.

FIG. 5 is a view showing the circuit structure of the respective stagesRS(1) to RS(n) of the gate driver 152. AS shown in the figure, eachstage has six TFTs (Thin Film Transistors) 21 to 26 as a basicstructure. Each of the TFTs 21 to 26 is constituted by an n channel MOStype field effect transistor. In addition, silicon nitride film is usedfor a gate insulating film and amorphous silicon film is used for asemiconductor layer.

A gate electrode and a drain electrode of the TFT 21 in each stage RS(k)are connected to a source electrode of the TFT 25 in each precedingstage RS(k−1), and the source electrode of the TFT 21 is connected tothe gate electrode of the TFT 22 in the same stage, the gate electrodeof the TFT 25, and the drain electrode of the TFT 24. The drainelectrode of the TFT 22 is connected to the source electrode of the TFT23 and the gate electrode of the TFT 26, and the constant voltage Vss issupplied to the source electrode of the TFT 22 and the source electrodeof the TFT 24. A power supply voltage vdd is supplied to the gateelectrode and the drain electrode of the TFT 23; the signal CK1, to thedrain electrode of the TFT 25 in the odd-numbered stage; and the signalCK2, the drain electrode of the TFT 25 in the even-numbered stage. Thesource electrode of the TFT 25 in each stage is connected to the drainelectrode of the TFT 26, and the constant voltage Vss is supplied to thesource electrode of the TFT 26. An output signal OUTk+1 of the nextstage is inputted to the gate electrode of the TFT 24.

FIG. 6 is a schematic block diagram showing an example of an invertedstagger type transistor applied suitably constructing to the respectiveTFTs 21 to 26 of the shift register according to the embodiment of thepresent invention, and FIG. 7 is a cross-sectional view taken along theline VII—VII in FIG. 6.

The inverted stagger type transistor is constituted by: a gate electrode72 formed on an insulating substrate 19 made of, e.g., glass in thedisplay area 151 (FIG. 3); a gate insulating film 16 provided on thegate electrode 72 and the insulating substrate 19; a semiconductor layer61 which is provided so as to be opposed to the gate electrode 72 andconsists of, e.g., amorphous silicon; block insulating films 64a, 64band 64c which are arranged in parallel so as to be separated from eachother on the semiconductor layer 61; an impurity dope layer 69a whichextends over one end portion of the block insulating film 64a in thechannel length direction and is provided on the semiconductor layer 61;an impurity dope layer 69b which extends over the other end portion ofthe block insulating film 64a in the channel length direction and oneend of the block insulating film 64b in the channel length direction andis provided on the semiconductor layer 61; an impurity dope layer 69cwhich extends over the other end portion of the block insulating film64b in the channel length direction and one end portion of the blockinsulating film 64c in the channel length direction is provided on thesemiconductor layer 61; an impurity dope layer 69d which extends overthe other end portion of the block insulating film 64c in the channellength direction and is provided on the semiconductor layer 61; a sourceelectrode 65 which is provided on each of the impurity dope layer 69a,the impurity dope layer 69b, the impurity dope layer 69c, and theimpurity dope layer 69d; a drain electrode 66; a source electrode 67; adrain electrode 68; and an interlayer insulating film 15 formed so as tocover the gate insulating film 16, the block insulating films 64a, 64band 64c, the source electrodes 65 and 67 and the drain electrodes 66 and68.

The gate electrode 72, and the source and drain electrodes 65 to 68 aremade of material selected from chrome, a chrome alloy, aluminium and analuminium alloy. The impurity dope layers 69a, 69b,69c and 69d are madeof amorphous silicon in which n type impurity ions are doped. Thesemiconductor layer 61 has a single layer structure existing in an areaindicated by hatching in the form of a grid.

Description will now be given as to the actions of the respective TFTs21 to 26 of this shift register. Since each stage has substantially thesame structure, the first stage RS(1) is exemplified.

The start signal Dst is supplied to the gate and the drain (electrode)of the TFT 21. The source (electrode) of the TFT 21 is connected to thegate (electrode) of the TFT 25, the gate of the TFT 22 and the source ofthe TFT 24. The TFT 25 is turned on when a node of a wiring Ca(1)between the TFT 25 and the source of the TFT 21 is on the high level.The clock signal CK1 is supplied to the drain of the TFT 25, and the TFT25 itself is turned on. Further, this signal is outputted as the outputsignal OUT1 of this stage RS(1) when the TFT 26 is in the OFF state.

The power supply Vdd is supplied to the gate and the source of the TFT23. When the source potential is sufficiently low with respect to thepower source voltage Vdd, the TFT 23 is turned on and outputs the powersupply voltage Vdd from the source. The voltage outputted from thesource of the TFT 23 is supplied to the drain of the TFT 22, and the TFT23 functions as a load so that the power supply voltage Vdd is suppliedto the TFT 22. The TFT 22 is turned on when the node of the wiring Ca(1)between the TFT 22 and the source of the TFT 21 is on the high level.The TFT 22 then emits the power supply voltage Vdd supplied through theTFT 23 from the wiring of the reference voltage Vss which is a lowervoltage.

When the TFT 22 is in the OFF state, the TFT 26 is turned on by thepower supply voltage Vdd fed through the TFT 23 and sets the voltagelevel of the output signal OUT1 as the reference voltage Vss.Furthermore, when the TFT 22 is in the ON state, the TFT 26 is turnedoff, and the voltage level of the clock signal CK1 becomes the voltagelevel of the output signal OUT1 at this time. The TFT 24 is turned on byan output signal OUT2 of a subsequent stage RS(2), and the potential ofthe node of the wiring Ca between the source of the TFT 21, the gate ofthe TFT 25 and the gate of the TFT 22 changes to the reference voltageVss.

The structure of the odd-numbered stages RS(2t+1) (t: an integer of 1 ton/2) excluding the first stage is the same as that of the first stageRS(1) except that the output signal OUT(2t) of the preceding stageRS(2t) is supplied to the gate and the drain of the TFT 21. Thestructure of the even-numbered stages RS(2t+2) (t: an integer of 0 ton/2) is the same as that of the first stage RS(1) except that an outputsignal OUT(2t+1) of the preceding stage RS(2t+1) is supplied to the gateand the drain of the TFT 21 and the clock signal CK2 is supplied to thedrain of the TFT 25 instead of the clock signal CK1. Moreover, althoughthe reset signal Dend fed to the gate of the TFT 24 of the last dummystage RS(n+2) is supplied from the controller 150, an output signal OUT3of the third stage RS(3) in the next scanning may be used instead.

Description will now be given as to the specific design of each stage ofthe shift register, especially how to set the relative dimension of theTFTs 21 to 26.

In the semiconductor layer 61 of each of the TFTs 21 to 26, the channelarea in which the drain electric current flows is determined as arectangle having two adjacent sides defined by a channel length L₁ and achannel width W₁, a rectangle having two adjacent sides defined by achannel length L₂ and the channel width W₁, and an orthogon having twoadjacent sides defined by a channel length L₃ and the channel width W₁.Incidentally, as to an optimum value for a later-described value (W/L)of the respective TFTs 21 to 26, all the TFTs 21 to 26 which are roughlydifferent from each other do not need to have the same structure as thatshown in FIGS. 6 and 7, and a number of channel areas of thesemiconductor layer 61 may be increased as a channel length L₄, achannel length L₅, . . . . Further, in case of a TFT having a smallvalue (W/L), a number of the three channel areas constituted by thechannel length L₁ to the channel length L₃ may be reduced to two orlower.

The drain electric current Ids flowing through this transistor can beexpressed by the following formula.Ids (W₁/L₁+W₁/L₂+W₁/L₃)=Σ(W/L)

Here, if L₁=L₂=L₃ is set, Σ(W/L)=3W₁/L₁ is obtained.

In the present invention, the relative value of the value Σ(W/L) of eachof the TFTs 21 to 26 is optimized to realize the shift register whichdoes not erroneously operate even in the high-temperature environment.In the following description, the value Σ(W/L) is simplified and writtenas the value (W/L). Therefore, the value (W/L) means Σ(W/L) as describedabove if there are a plurality of channel areas. Here, a signal on avoltage level whose high level and low level largely differ from eachother is supplied from outside to the drains of the TFT 21 and the TFT25, and this signal must be outputted from their sources. Thus, thevalue (W/L) of their size is restricted in a given range.

Here, to the TFT 25 is supplied the clock signal CK1 or the clock signalCK2 having a large voltage difference between the low level and the highlevel, and on level (high level) output signals OUT1 to OUTn must beoutputted as gate signals having rectangular waves with less noise.Therefore, the level of the output signals OUT1 to OUTn must besufficiently increased in a short period of time. Accordingly, thebootstrap effect must be generated to cause the high drain electriccurrent to flow in a short period of time. Therefore, as (W/L), a largervalue is desirable. In addition, since the parasitic capacitancesbetween the gate and the source and between the gate and the drain ofthe TFT 25 must be increased in order to obtain the larger bootstrapeffect, the relatively larger size of the transistor is desirable forthe TFT 25.

On the other hand, although the start signal Dst having a large voltagedifference between the low level and the high level or an output signalof the preceding stage is supplied to the TFT 21 and outputted to thewiring Ca, it is unnecessary to increase the potential level of the nodeof the wiring Ca in a short period of time as will be described later.Therefore, a considerably large value is required for the TFT 25, butthe value for the TFT 21 does not have to be increased as the value(W/L) for the TFT 25. Thus, when the TFT 21 is used for the gate driverof the liquid crystal display, that TFT can function even if its valueis approximately ⅓ of that of the TFT 25.

Since both the TFT 23 and the TFT 22 are used for switching of the TFT26 and do not supply output signals, the high drain electric currentdoes not have to flow in a short period of time, and a steep and largepotential change such as that in the bootstrap effect is not observed ineach terminal. Therefore, the influence of the erroneous operation ofthe shift register is small even if the value (W/L) of each of the TFTs23 and 22 is set smaller than that of each of the TFTs 21 and 25. It is,however, preferable that the TFT 23 has a value (W/L) larger than 1/20of the value of the TFT 25, and more desirable that the TFT 23 has avalue (W/L) which is not less than ⅕ of the value of the TFT 25.

Since the influence of the TFT 22 to the output signals OUT1 to OUTn issmallest, it is desirable that the value (W/L) of the TFT 22 is thesmallest value among the values (W/L) of the other TFTs 21 and 23 to 26.

The voltage of the TFT 26 must be forcibly changed from the high levelto the reference voltage Vss which is on the low level so that the drainelectric current can rapidly flow, when the output signals OUT1 to OUTnare switched from the ON level (high level) to the OFF level (lowlevel). Thus, the larger value (W/L) is desirable for the TFT 26.

Although it is desirable that the gate voltage of the TFT 25 in the OFFlevel period is on a constant low level, the noise may bedisadvantageously added to the gate signal (low level of the outputsignals OUT1 to OUTn) in the OFF level period, which are supplied to thegate line GL, due to a leak electric current of the TFT 25 which isgenerated because the gate voltage of the TFT 25 oscillates inaccordance with an amplitude of the low level and the high level of theclock signal CK1 or CK2. Further, since the OFF level period of eachgate line GL is overwhelmingly longer than the ON level period, theabove-described action greatly affects the liquid crystal display. Itis, therefore, desirable to set the value (W/L) of the TFT 26 equal toor above that of the TFT 25 in order to suppress the noise added to thegate line GL during the OFF level period and stabilize the low levelvoltage.

The TFT 21 sets the TFT 25 on the ON level (high level), whereas the TFT24 sets the TFT 25 on the OFF level (low level). Thus, it is desirablethat the value (W/L) of the TFT 24 is substantially equal to that of theTFT 21.

In order to prevent the malfunction of the shift register even underhigh-temperature conditions, it is desirable to set the values (W/L) ofthe TFTs 21 to 26 as high as possible. However, the entire area of theshift register increases as the values of the TFTs 21 to 26 are sethigher. Therefore, taking the environment conditions for use or thecircuit arrangement into consideration, setting each value (W/L) in theabove-described condition range can suffice. The relationship betweenthe value (W/L) of each of the TFTs 21 to 26 and the durable temperaturewill be further considered in accordance with the later-describedembodiment.

Description will now be given as to the operation of the shift registeraccording to this embodiment. FIG. 8 is a timing chart showing theoperation of the shift register illustrated in FIG. 4.

In a period from a timing T0 to another timing T1, when the start signalDst rises to the high level, the TFT 21 of the first stage RS(1) isturned on, and this signal is outputted from the drain of the TFT 21 tothe source. As a result, the node potential of the wiring Ca(1) of thefirst stage RS(1) rises to the high level. Consequently, the gatevoltages of the TFT 25 and the TFT 22 rise to the high level, therebyturning on the TFTs 25 and 22. Further, when the TFT 22 is turned on,the power supply voltage Vdd fed through the TFT 23 is no longersupplied to the gate of the TFT 26 and the TFT 26 is turned off. In thisperiod, since the clock signal CK1 is on the low level, it can beunderstood that the level of the output signal OUT1 remains on the lowlevel.

Subsequently, at the timing T1, when the clock signal CK1 changes to thehigh level, this signal is outputted from the drain of the TFT 25 of thefirst stage RS(1) to the source, and the level of the output signal OUT1varies to the high level. At this time, since the potential of thewiring Ca(1) raises to a high voltage due to the bootstrap effect, itreaches to a saturation gate voltage of the TFT 25, and the outputsignal OUT1 has the potential substantially equal to that of the clocksignal CK1 on the high level. Thereafter, when the clock signal CK1falls to the low level in a period from the timing T1 to the next timingT2, the output signal OUT1 approximates the low level.

Furthermore, in the period from the timing T1 to the next timing T2, theTFT 21 of the second stage RS(2) is turned on by the output signal OUT1of the first stage RS(1) which has risen to the high level, and thepotential of the node of the wiring Ca(2) reaches the high level. As aresult, the TFT 25 and the TFT 22 of the second stage RS(2) are turnedon, and the TFT 26 is turned off.

Subsequently, at the timing T2, when the clock signal CK2 changes to thehigh level, this signal is outputted from the drain of the TFT 25 of thesecond stage RS(2) to the source, and the level of the output signalOUT2 changes to the high level. At this time, since the potential of thenode of the wiring Ca(2) rises to a high voltage due to the bootstrapeffect, it reaches the saturation gate voltage of the TFT 25, and theoutput signal OUT2 has the potential substantially equal to that of theclock signal CK2 on the high level. Moreover, when the output signalOUT2 on the high level is supplied to the gate of the TFT 24 of thefirst stage RS(1), the TFT 24 is turned on in the first stage RS(1), andthe high level voltage of the node of the wiring CA(1) becomes thereference voltage Vss. Thereafter, when the clock signal CK2 falls tothe low level in a period from the timing T2 to the next timing T3, theoutput signal OUT2 approximates the low level.

In addition, in a period from the timing T2 to the next timing T3, TFT21 of the third stage RS(3) is turned on by the output signal OUT2 ofthe second stage RS(2) which has risen to the high level, and thepotential of the node of the wiring Ca(3) changes to the high level.Consequently, the TFTs 25 and 22 of the third stage RS(3) are turned on,and the TFT 26 is turned off.

Subsequently, in the timing T3, when the clock signal CK1 changes to thehigh level, this signal is outputted from the drain of the TFT 25 of thethird stage RS(3) to the source, and the level of the output signal OUT3varies to the high level. At this time, since the potential of thewiring Ca(3) rises to a high voltage due to the bootstrap effect, itreaches to the saturation gate voltage of the TFT 25, and the outputsignal OUT 3 has the potential substantially equal to that of the clocksignal CK1 on the high level. Additionally, when the output signal OUT3on the high level is supplied to the gate of the TFT 24 of the secondstage RS(2), the TFT 24 is turned on in the second stage RS(2), and thehigh level voltage of the wiring Ca(2) is set as the reference voltageVss. Subsequently, the output signals OUT1 to OUTn of the respectivestages similarly sequentially rise to the high level in one scanningperiod Q until the timing Tn (next timing T0). As described above, thehigh level potential of each of the output signals OUT1 to OUTn is notgradually decreased even if shifted to the next stage. Further, thestart signal Dst again rises to the high level after the one scanningperiod Q, and the above-mentioned operation is thereafter repeated inthe stages RS(1) to RS(n).

Although the node of the wiring Ca(n) remains on the high level afteroutputting the output signal OUTn on the high level in the last stageRS(n) of the gate line GL, the TFT 24 of the last stage RS(n) is turnedon by the output signal OUTn+1 of the dummy stage RS(n+1) whichcommences to be driven by the output signal OUTn, and the node of thewiring Ca(n) changes to have the reference voltage Vss. Similarly, theTFT 24 of the dummy stage RS(n+1) is turned on by the output signalOUTn+2 of the dummy stage RS(n+2), and the node of the wiring Ca(n+1)varies to have the reference voltage Vss. Further, the node of thewiring Ca(n+2) of the dummy stage RS(n+2) changes from the high level tothe reference voltage Vss, when the reset signal Dend on the high levelis supplied to the TFT 24 of the dummy stage RS(n+2).

Although the above-described shift register ideally operates inaccordance with the timing chart shown in FIG. 8, the possibility of amalfunction of the shift register becomes higher as the temperatureincreases because the characteristic of the TFTs 21 to 26 changes as thetemperature increases. That is, there increases the possibility ofoccurrence of a malfunction or a disabled normal operation that thepotential of the wiring Ca which is in the floating state between thegate of the TFT 25 and the source of the TFT 21 increases insynchronization with the clock signal CK1 or CK2 and the TFTs 25 and 22are turned on.

Description will now be given on how a malfunction of theabove-mentioned shift register affects an electronic apparatus usingthis shift register. Although the above-described shift register is usedas a driver for, e.g., a liquid crystal display or an imaging device,the case where the shift register is used in the liquid crystal displaywill be explained herein.

The gate driver 152 to which the shift register according to thisembodiment is applied sequentially selects the gate line GL inaccordance with the control signal group Gcnt from the controller andoutputs a predetermined voltage. This control signal group Gcnt includesthe clock signals CK1 and CK2, the start signal Dst, the power supplyvoltage Vdd and the reference voltage Vss described above.

Description will now be given hereinafter on how the operation of theliquid crystal display varies in the case where the gate driver 152 towhich the above shift register is applied normally functions and in thecase where the same erroneously operates. In the following description,it is assumed that the pixel TFT 161 and the drain driver 153 in thedisplay area 151 normally function without any malfunction.

When the gate driver 152 normally functions, the level of the voltageoutputted to the gate line GL from a plurality of stages except a stagewhich should essentially output the high level signal is suppressed tobe lower than that of a threshold voltage of the pixel TFT 161. Thesignal on the high level is outputted to the gate lines GL one by one bythe output signals sequentially supplied from the respective stages ofthe gate driver 152, and the pixel TFT 161 for the corresponding oneline is turned on.

The drain driver 153 fetches image data data supplied from thecontroller in accordance with each line and outputs a correspondingsignal to each drain line DL in accordance with a selection of the gateline GL. The signal outputted to the drain line DL in this manner iswritten in the pixel capacitance 162 through the pixel TFT 161 which isin the ON state. Moreover, the orientation state of the liquid crystalchanges in accordance with the signal written in the pixel capacitancevaries and a quantity of light to be transmitted is adjusted, therebydisplaying an image on a screen of the liquid crystal display.

On the other hand, when the gate driver 152 erroneously operates asdescribed above, the voltage outputted to the gate line GL from a stagewhich essentially should not output the high level signal approximatesor exceeds the threshold voltage of the pixel TFT 161, and the pixel TFT161 may accidentally cause the drain electric current to flow. In thiscase, the signal outputted from the drain driver 153 to the drain lineDL is also written in the pixel capacitance 162 in which a signal shouldnot be written through the pixel TFT 161, as well as the pixelcapacitance 161 in which a signal should be essentially written. As aresult, the orientation state of the liquid crystal differs from thetrue orientation state, and an image displayed on the liquid crystaldisplay becomes different from an image which should be primarilydisplayed.

As described above, in the shift register according to this embodiment,by setting the value (W/L) of each of the TFTs 21 to 26 in a range ofthe above-described conditions, the shift register can normally operatefor a long time even under the high-temperature conditions. Therefore,for example, in the liquid crystal display in which this shift registeris applied as the gate driver 152, the noise of the output signal fed tothe pixel TFT 161 of the liquid crystal display can be reduced, and datawhich should not be essentially written in the pixel capacitance 162 canbe prevented from being written. This improves the grade of an imagedisplayed on the liquid crystal display.

As the value (W/L) of each of the TFTs 21 to 26 increases, the shiftregister can normally operates even under the high-temperatureconditions. However, an area of the shift register becomes large.Further, since the display area 151 and the gate driver 152 are formedon the same substrate 19 in the above-described liquid crystal display,an area of the liquid crystal display device relatively becomes small.In particular, when the TFTs 21 to 26 are amorphous silicon TFTs, sinceone transistor size is large as compared with that in case ofpolysilicon TFTs or monocrystal silicon transistors, its influencenecessarily becomes great. Therefore, the largeness of the value (W/L)of each of the TFTs 21 to 26 is restricted. The preferable balance ofthe operation stability of the shift register and the value (W/L) ofeach of the TFTs 21 to 26 will be considered in the later-describedembodiment.

In cases where the value (W/L) of the TFT 21 is fixed at 120 and thevalue (W/L) of the TFT 25 is fixed at 320 as shown in Table 1, shiftregisters (A) to (J) having different values (W/L) of the TFTs 22 to 24and 26 were created as the shift register of the gate driver 152described in the above embodiment. In this connection, W/L of the TFT 21is determined as 120 because the shift register with the value (W/L) ofthe TFT 21 being 60 as a comparative example has a low drive capabilityand its lower limit of the temperature at which the malfunction occursis lower than that of the shift register with the value (W/L) of the TFT21 being 120. Here, the values (W/L) of the TFTs 21 and 25 are fixed forthe reason above-mentioned. Incidentally, it is desirable that the shiftregister normally operates in the environment with a temperature whichis not more than 65° C.

TABLE 1 DIMENSION RATIO OF CHANNEL WIDTH/CHANNEL LENGTH (W/L) SAMPLETFT21 TFT22 TFT23 TFT24 TFT25 TFT26 A 120 24 32 120 320 320 B 120 36 48120 320 480 C 120 48 64 120 320 640 D 120 12 16 120 320 320 E 120 48 64120 320 320 F 120 24 24 120 320 320 G 120 24 40 120 320 320 H 120 24 48120 320 320 I 120 24 32 80 320 320 J 120 24 32 120 320 320

Here, the channel lengths L of all the TFTs 21 to 26 in the table areset to 9 μm. A considerable difference from the shift register havingthe channel lengths L being all 9 μm was not obtained even though thechannel lengths L of the TFTs 25 and 26 were set to 12 μm and thechannel lengths L of the remaining TFTs 21 to 24 were set to 9 μm.

Ten types of shift registers indicated as (A) to (J) in Table 1 weredriven under the various temperature conditions, and their temperaturecharacteristics were examined. Table 2 shows its result. In Table 2, “G”represents that the shift register normally operated for a long periodof time under that temperature condition, and “NG” represents that themalfunction occurred when the shift register was driven for a longperiod of time under that temperature condition or the shift registerdid not operate.

TABLE 2 SAM- OUTER TEMPERATURE (° C.) PLE 25 35 45 55 60 65 70 75 80 8590 A G G G G G G G G NG NG NG B G G G G G G G G G G G C G G G G G G G GG G G D G G G G G G NG NG NG NG NG E G G G G G G G G G G G F G G G G G GNG NG NG NG NG G G G G G G G G G NG NG NG H G G G G G G G G G G G I G GG G G G NG NG NG NG NG J G G G G G G G G G G G

From this result, the following respects can be derived.

As apparent from (A), (B) and (C) in Tables 1 and 2, the value (W/L) ofthe TFT 26 can be set equal to or larger than the value (W/L) of the TFT25 in order to normally operate the shift register up to the temperature65° C. When the value (W/L) of the TFT 26 is set larger than the value(W/L) of the TFT 25, the shift register can normally operate up to 90°C. depending on the values (W/L) of the TFTs 23 and 22, which is morepreferable.

As apparent from (A), (D) and (E) in Tables 1 and 2, the value (W/L) ofthe TFT 23 can be set larger than 1/20 of the value (W/L) of the TFT 25in order to normally operate the shift register up to 65° C. When thevalue (W/L) of the TFT 23 is set to approximately ⅕ of the value (W/L)of the TFT 25, the shift register can normally operate up to 90° C.,which is more preferable.

As apparent from (A), (F), (G) and (H) in Tables 1 and 2, setting thevalue (W/L) of the TFT 23 to be larger than the value (W/L) of the TFT22 can suffice the normal operation of the shift register up to 65° C.When the value (W/L) of the TFT 23 is increased to be approximatelytwofold of the value (W/L) of the TFT 22, the shift register cannormally operate up to 90° C., which is more preferable.

As apparent from (A), (I) and (J) in Tables 1 and 2, setting the value(W/L) of the TFT 24 to be larger than ⅔ of the value (W/L) of the TFT 21can suffice the normal operation of the shift register up to 65° C. Whenthe value (W/L) of the TFT 24 is increased to approximately 4/3 of thatof the TFT 21, the shift register can preferably normally operate up to90° C.

Further, when the value (W/L) of the TFT 21 is set smaller than thevalue (W/L) of each of the TFTs 25 and 26 and larger than the value(W/L) of each of the TFTs 23 and 22 and the value (W/L) of the TFT 24 isset smaller than the value (W/L) of each of the TFTs 25 and 26 andlarger than the value (W/L) of each of the TFTs 23 and 22, the normaloperation can to be easily obtained, and the comprehensive duration oflife is long in the environment at the temperature of 80° C.

The present invention is not restricted to the above-describedembodiment, and various modifications and applications are enabled. Amodification of the above-described embodiment which can be applied tothe present invention will now be described hereinafter.

Although the respective stages RS(1), RS(2), . . . of the shift registerare constituted by the six TFTs 21 to 26 in the above-describedembodiment, the similar advantages was obtained with seven shiftregisters having the structure of respective stages RS(1), RS(2), . . ., such as shown in FIG. 9. The value (W/L) of the TFT 27 added herein is2, and the voltage Vdd1 is determined to be equipotential with the powersupply voltage Vdd of the above-described embodiment. Further, theconfiguration is similar to that of the shift register shown in FIG. 4except that the voltage Vdd2 is lower than the voltage Vdd1. It is to benoted that the TFT 23 illustrated in FIG. 9 can be replaced with aresistance device other than the transistor.

In the above-described embodiment, although the shift register isconstituted by combinations of the amorphous silicon TFTs 21 to 26 whichare the field effect transistors, they may be substituted by polysilicontransistors other than the amorphous silicon TFTs. Moreover, althoughthe TFTs 21 to 26 constituting the shift register are of the n channeltype in the above example, all the TFTs may be of the p channel type. Atthis time, the high and low levels of each signal may be inverted fromthose in the case where the TFTs which are of the n channel type areused.

In the above-described embodiment, although the gate driver 152 of theliquid crystal display is exemplified as an application example of theshift register, the shift register can be also applied to a driver ofany other display unit, e.g., an organic EL display unit or a plasmadisplay panel. In addition, the shift register can be applied as adriver for driving a photosensor such as a fingerprint sensor in which aplurality of pixels are vertically and horizontally arranged in apredetermined order, as well as a display unit. In this case, the gradeof a picked-up image can be improved. Additionally, the shift registeris not only used as such a driver but it can be also applied to the casewhere serial data is converted into parallel data in a data processor.

FIG. 10 is a block diagram showing the structure of an imaging apparatushaving an imaging device, in which a double gate transistor is appliedas a photosensor. This imaging apparatus is used as, for example, afingerprint sensor and constituted by a controller 70, an imaging area71, a tope gate driver 72, a bottom gate driver 73, and a drain driver74.

The imaging area 71 is constituted by a plurality of double gatetransistors 81 arranged in the matrix form. A top gate electrode 91 ofthe double gate transistor 81 is connected to a top gate line TFL; abottom gate electrode 92, a bottom gate line BGL; a drain electrode 93,a drain line DL; and a source electrode 94, an earthed ground line GrL,respectively. A back light for emitting a light ray having a wavelengthrange for exciting the semiconductor layer of the double gate transistor81 is mounted under the imaging area 71.

When the voltage applied to the top gate electrode 91 is +25 (V) and thevoltage applied to the bottom gate electrode 92 is 0 (V), the positivehole accumulated in the semiconductor layer and the gate insulating filmconsisting of silicon nitride arranged between the top gate electrode 91and the semiconductor layer is emitted, and the double gate transistor81 constituting the imaging area 71 is reset. The double gate transistor81 enters the photosensing state in which the voltage between the sourceelectrode 94 and the drain electrode 93 is 0 (V), the voltage applied tothe top gate electrode 91 is −15 (V), the voltage applied to the bottomgate electrode 92 is 0 (V) and the positive hole in a pair of thepositive hole and the electron generated by incoming radiation of thelight to the semiconductor layer is accumulated in the semiconductorlayer and the gate insulating film. A quantity of the positive holeaccumulated in this period depends on a quantity of light.

In this photosensing state, although the back light emits the lighttoward the double gate transistor 81, the bottom gate electrode 92positioned below the semiconductor layer of the double gate transistor81 prevents transmission of the light as it stands, the sufficientcarrier is not generated in the semiconductor layer. At this time, whena finger is put on the insulating film above the double gate transistor81, the light reflected by the insulating film and the like is lesslikely to be incident upon the semiconductor layer of the double gatetransistor 81 directly below recessions of the finger (corresponding togrooves defining a fingerprint shape).

As described above, when a quantity of the incident light is small, asufficient quantity of the positive hole is not accumulated in thesemiconductor layer, the voltage applied to the top gate electrode 91 is−15 (V) and a voltage applied to the bottom gate electrode 92 become +10(V), a depletion layer spreads in the semiconductor layer, and the nchannel is pinched off, resulting in the high resistance of thesemiconductor layer. On the other hand, the light reflected by theinsulating film and the like is incident upon the semiconductor layer ofthe double gate transistor 81 directly below convex portions(protrusions between grooves of a finger) of the finger in thephotosensing state, and a sufficient quantity of positive holes isaccumulated in the semiconductor layer. In this state, when such avoltage is applied, the accumulated positive hole is attracted to thetop gate electrode 91 and held. As a result, the n channel is formed onthe bottom gate electrode 92 side of the semiconductor layer, resultingin the low resistance of the semiconductor layer. A difference inresistance value of the semiconductor layer in the reading state appearsas a change in potential of the drain line DL.

The top gate drive 72 is connected to the top gate line TGL in theimaging area 71 and selectively outputs a signal of +25 (V) or −15 (V)to each top gate line TGL in accordance with the control signal groupTcnt from the controller 70. The top gate driver 72 has the structurewhich is substantially the same as that of the shift registerconstituting the gate driver 152, the top gate driver 72 and the bottomgate driver 73 shown in FIG. 4 or 10 except a difference in level of theoutput signal, a difference in level of the input signal according tothe output signal and a difference in phase of output signal and theinput signal.

The bottom gate driver 73 is connected to the bottom gate line BGL inthe imaging area 71 and outputs a signal of +10 (V) or 0 (V) to eachbottom gate line BGL in accordance with the control signal group Bcntfrom the controller 70. The bottom gate driver 73 has the structurewhich is substantially the same as that of the shift registerconstituting the gate driver 152, the top gate driver 72 and the bottomgate driver 73 shown in FIG. 4 or 10 except a difference in level of theoutput signal, a difference in level of the input signal according tothe output signal, and a difference in phase of the output signal andthe input signal.

The drain driver 74 is connected to the drain line DL in the imagingarea 71, and outputs a constant voltage (+10 (V)) to all the drain linesDL in a later-described predetermined period in accordance with thecontrol signal group Dcnt from the controller 70 in order to pre-chargethe electric charge. The drain driver 74 reads the potential of eachdrain line DL which varies depending on whether a channel is formed inaccordance with incidence or non-incidence of the light upon thesemiconductor layer of the double gate transistor 81 in a predeterminedperiod after pre-charge, and supplies the obtained result to thecontroller 70 as image data DATA.

The controller 70 controls the top gate driver 72 and the bottom gatedriver 73 in accordance with the control signal groups Tcnt and Bcnt,respectively, and outputs a signal on a predetermined level at apredetermined timing from the both drivers 72 and 73. As a result, eachline in the imaging area 71 sequentially enters the reset state, thephotosensing state and reading state. Further, the controller 70 causesthe drain driver 74 to read a change in potential of the drain line DLby the control signal group Dcnt and sequentially fetches these changesas the image data DATA.

FIG. 11 is a view showing the circuit structure of the shift registerapplied as a gate driver 152, a top gate driver 72, and a bottom gatedriver 73 shown in FIGS. 3 and 10. As shown in the figure, this shiftregister is constituted by n stages RS(1) to RS(n) (n: an even number)whose number is equal to that of the gate lines GL in the display area151.

When applied as the gate driver 152, to this shift register are suppliedthe clock signals CK1 and CK2, the power supply voltage Vdd, thereference voltage Vss (<Vdd), the start signal Dst, and the reset signalDend as the control signal group Gcnt from the controller 150. Amongthese voltages and signals, the power supply voltage Vdd and thereference voltage Vss are supplied to all the stages RS(1) to RS(n); theclock signal CK1, the odd-numbered stages RS(1), RS(3), . . . , RS(n−1);the clock signal CK2, the even-numbered stages RS(2), RS(4), . . . ,RS(n); the start signal Dst, only the first stage RS(1); and the resetsignal Dend, only the n-th stage RS(n).

The structures of the respective stages are substantially the same.Thus, giving description as to the first stage RS(1) as an example, thestage RS(1) has six TFTs 1 to 6 consisting of a-Si semiconductor layerssimilar to the TFT 161. The TFTs 1 to 6 are field effect transistorswhich area of the same channel type (here, an n-channel type).

The start signal Dst is supplied to the gate of the TFT 1. The powersource voltage Vdd is supplied to the drain of the TFT 1. The source ofthe TFT 1 is connected to the gate of the TFT 2, the gate of the TFT 5,and the drain of the TFT 6. The wiring surrounded by and connected withthe source of the TFT 1, the gate of the TFT 2, the gate of the TFT 5and the drain of the TFT 6 is referred to as a node A1 (wirings will bereferred to as A2 to An in the second and the subsequent stages). Whenthe start signal Dst raises to the high level and the TFT 1 is turnedon, the voltage which is equipotential with the power supply voltage Vddis outputted from the source, thereby applying the voltage to the nodeA1.

The clock signal CK1 is supplied to the drain of the TFT 2. When the TFT2 is in the ON state, the level of the clock signal CK1 is outputted asthe output signal OUT1 from the source to the first gate line GLsubstantially without any change.

The power supply voltage Vdd is supplied to the gate and the drain ofthe TFT 4, and the TFT 4 is constantly in the ON state. The TFT 4functions as a load when supplying the power supply voltage Vdd, andsupplies the power supply voltage Vdd to the drain of the TFT 5substantially without any change. The TFT 4 can be replaced with theresistance device other than the TFT. The reference voltage Vss issupplied to the source of the TFT 5. When the TFT 5 is turned on, theelectric charge accumulated between the source of the TFT 4 and thedrain of the TFT 5 is discharged and the gate voltage of the TFT 3 isset as the reference voltage Vss.

The gate of the TFT 3 is connected to the source of the TFT 4 and thedrain of the TFT 5. When the TFT 5 is in the OFF state, the TFT 3 isturned on by the power supply voltage vdd fed through the TFT 4. Whenthe TFT 5 is in the ON state, since the electric charge accumulated inthe wiring between source of the TFT 4 and the TFT 5 is discharged, andthe gate voltage of the TFT 3 falls to the low level, thereby turningoff the TFT 3.

The output signal OUT2 of the second stage RS(2) which is the subsequentstage is supplied to the gate of the TFT 6. The drain of the TFT 6 isconnected to the node A1, and the reference voltage Vss is supplied tothe source. When the output signal OUT2 rises to the high level, the TFT6 is turned on to discharge the electric charge accumulated in the nodeA1.

The structure of the odd-numbered stages RS(3), RS(5), . . . , RS(n−1)other than the first stage is the same as that of the first stage RS(1)except that the output signals OUT2, OUT4, . . . , OUTn−2 of thepreceding stages RS(2), RS(4), . . . , RS(n−2) are supplied to the gateof the TFT 1.

The structure of the even-numbered stages RS(2), RS(4), . . . , RS(n−2)other than the n-th stage is the same as that of the first stage RS(1)except that the output signals OUT1, OUT3, . . . , OUTn−3 of thepreceding stages RS(1), RS(3), . . . , RS(n−3) are supplied to the gateof the TFT 1. The structure of the n-th stage RS(n) is the same as thatof other even-numbered stages RS(2), RS(4), . . . , RS(n−2) except thatthe reset signal Dend is supplied to the gate of the TFT 6.

Moreover, the shift registers constituting the gate driver 152, the topgate driver 72 and the bottom gate driver 73 are configured bycombinations of the TFTs 1 to 6, and the TFTs 1 to 6 have substantiallythe same structure as that of the TFT 161 included in the display area151. Therefore, the gate driver 152, the top gate driver 72 and thebottom gate driver 73 can be collectively formed on the substrate on theTFT 161 side of the display area 151 by the same process.

The operation of the digital still camera according to this embodimentwill now be described. Before explaining the overall operation, theoperation of the shift register constituting the above-described gatedriver 152 will be first explained with reference to a timing chart ofFIG. 12. When the shift register is used as the gate driver 152,respective control signals are all supplied from the controller 150 asthe control signal group Gcnt.

In this timing chart, the high level of each of the clock signals CK1and CK2, the start signal Dst and the reset signal Dend is equal to thepower supply voltage Vdd. On the other hand, the low level of thesesignals is equal to the reference voltage Vss. One scanning period Q isone horizontal period in the display portion 210.

In addition, before starting the shift operation in accordance with thistiming chart (before T0), all of the output signals OUT1 to OUTn are onthe low level. Additionally, in all of the stages RS(1) to RS(n), noelectric charge is accumulated in the nodes A1 to An, and the TFTs 2 and5 are in the ON state while the TFT 3 is in the OFF state.

In a period from the timing T0 to another timing Ti, when the startsignal Dst rises to the high level, the TFT 1 of the first stage RS(1)is turned on, and the power supply voltage Vdd is outputted from thedrain of the TFT 1 to the source. As a result, the electric charge isaccumulated in the node A1 of the first stage RS(1), and its potentialrises to the high level, thereby turning on the TFTs 2 and 5. When theTFT 5 is turned on, the electric charge accumulated between the sourceof the TFT 4 and the drain of the TFT 5 is discharged, thereby turningoff the TFT 3. In this period, the TFT 2 of the first stage RS(1) isturned on, but the clock signal CK1 remains on the low level. Thus, thelevel of the output signal OUT1 remains as the low level.

Subsequently, in the timing T1, when the clock signal CK1 changes to thehigh level, this signal is outputted from the drain of the TFT 2 of thefirst stage RS(1) to the source, and the level of the output signal OUT1varies to the high level. At this time, since the potential of the nodeA1 increases to approximately twofold of the power supply voltage Vdd bythe so-called bootstrap effect and reaches the saturation gate voltageof the TFT 2, the drain electric current of the TFT 2 becomes asaturation electric current, and the level of the output signal OUT1rapidly becomes substantially equipotential with the high level of theclock signal CK1. That is, the high level of the output signal OUT1becomes nearly the power supply voltage Vdd. Thereafter, in a periodfrom the timing T1 to the timing T2, when the clock signal CK1 falls,the output signal OUT1 shifts to the low level.

Further, in a period from the timing T1 to the timing T2, the TFT 1 ofthe second stage RS(2) is turned on by the output signal OUT1 of thefirst stage RS(1) which has risen to the high level. Consequently,outputting the power supply voltage Vdd from the source of the TFT 1 ofthe second stage RS(2) causes the potential of the node A2 to change tothe high level, and the TFTs 2 and 5 of the second stage RS(2) areturned on, thereby turning off the TFT 3.

Subsequently, in the timing T2, when the clock signal CK2 changes to thehigh level, this signal is outputted from the drain of the TFT 2 of thesecond stage RS(2) to the source, and the level of the output signalOUT2 varies to the high level. Consequently, the TFT 6 of the firststage RS(1) is now turned on, and the electric charge accumulated in thenode A1 is discharged through the TFT 6 to obtain the reference voltageVss. Therefore, the output signal OUT1 maintains the low level state,and the TFTs 2 and 5 of the first stage RS(1) are thereby turned off,and the TFT of the same is turned on. Accordingly, the potential of theoutput signal OUT1 surely becomes the reference voltage Vss, and thisstate continues at least until the timing Tn+1. Thereafter, when theclock signal CK2 falls in a period from the timing 2 to the timing T3,the output signal OUT2 falls to the low level.

Furthermore, in the period from the timing T2 to the timing T3, the TFT1 of the third stage RS(3) is turned on by the output signal OUT2 of thesecond stage RS(2) which has risen to the high level. As a result,outputting the power supply voltage vdd from the source of the TFT 1 ofthe third stage RS(3) causes the potential of the node A3 to change tothe high level, and the TFTs 2 and 5 of the third stage RS(3) are turnedon, thereby turning off the TFT 3.

Subsequently, in the timing T3, when the clock signal CK1 changes to thehigh level, this signal is outputted from the drain of the TFT 2 of thethird stage RS(3) to the source, and the level of the output signal OUT3varies to the high level. Consequently, the TFT 6 of the second stageRS(2) is now turned on, and the electric charge accumulated in the nodeA2 is discharged through the TFT 6 without using the TFT 1 of the secondstage RS(2) and the TFT 3 of the first stage RS(1) to obtain thereference voltage Vss. Therefore, the low level state of the outputsignal OUT1 is maintained, and the TFTs 2 and 5 of the second stageRS(2) are thereby turned off, meanwhile the TFT 3 is turned on. That is,since the gate voltage of the TFT 2 falls to the low level and the TFT 3is turned on in the second stage RS(2), the potential of the outputsignal OUT2 assuredly becomes the reference voltage Vss, and this statecontinues at least until the timing Tn+1. Thereafter, in a period fromthe timing T2 to the timing T3, when the clock signal CK1 falls, thelevel of the output signal OUT3 becomes the low level.

In addition, in a period from the timing T3 to another timing T4, theTFT 1 of the fourth stage RS(4) is turned on by the output signal OUT3of the third stage RS(3) which has risen to the high level. As a result,outputting the power supply voltage vdd from the source of the TFT 1 ofthe fourth stage RS(4) causes the potential of the node A4 to rise tothe high level, and the TFTs 2 and 5 of the fourth stage RS(4) areturned on, meanwhile the TFT 3 is turned off.

Thereafter, when the fourth and the subsequent stages RS(4), RS(5), . .. perform the operation similar to the above in accordance with each onescanning period Q, the output signals OUT4, OUT5, vary to the high levelfor each predetermined period in the one scanning period Q. Furthermore,in a period from the timing Tn−1 to the timing Tn, the TFT 1 of the n-thstage RS(n) is turned on by the output signal OUTn−1 of the n−1-th stageRS(n−1) which has risen to the high level. As a result, outputting thepower supply voltage vdd from the source of the TFT 1 of the n-th stageRS(n) causes the potential of the node An to change to the high level,and the TFTs 2 and 5 of the n-th stage RS(n) are turned on meanwhile theTFT 3 is turned off.

Subsequently, in the timing Tn, when the clock signal CK2 rises to thehigh level, this signal is outputted from the drain of the TFT 2 of then-th stage RS(n) to the source, and the level of the output signal OUTnchanges to the high level. Thereafter, when the clock signal CK2 fallsuntil the timing Tn+1, the output signal OUTn changes to the low level.

Then, in the timing Tn+1, the level of the reset signal Dend now changesto the high level. As a result, when the TFT 1 of the n-th stage RS(n)is turned on, the electric charge accumulated n the node A2 isdischarged so that the TFTs 2 and 5 of the second stage RS(2) are turnedoff and the TFT 3 is turned on. Further, no electric charge isaccumulated in the nodes A1 to An in all of the stages RS(1) to RS(n)until the start signal Dst on the high level is subsequently supplied,and the TFTs 2 and 5 are in the ON state while the TFT 3 remains in theOFF state.

Description will now be given as to how the potentials of the gate, thedrain and the source of one TFT 1 change while the output signal shiftsfrom the first stage RS(1) to the n-th stage RS(n) taking the TFT 1 ofthe third stage RS(3) for instance. The lower three sections in FIG. 12show changes in potential level of the gate, the drain and the source ofthe TFT 1 of the third stage RS(3).

As shown in the figure, the gate voltage of the TFT 1 rises to the highlevel (substantially Vdd) only when the output signal OUT2 of the secondstage RS(2) is on the high level in a period from the timing T2 to thetiming T3. Since the power supply voltage Vdd is constantly supplied tothe drain of the TFT 1, the drain voltage is constantly the power supplyvoltage vdd. When the electric charge is accumulated in the node A3 inthe timing T2, the source voltage of the TFT 1 changes to a voltagelevel which is lower than vdd by its threshold voltage. When the clocksignal CK1 is on the high level in a period from the timing T3 to thetiming T4, the source voltage reaches the level which is approximatelytwofold of the power supply voltage Vdd by the above-described bootstrapeffect. On and after change of the output voltage of the fourth stageRS(4) to the high level in the timing T4, the source voltage again fallsto the low level.

As described above, the gate voltage of the TFT 1 of the k-th stageRS(k) in one scanning of the shift register is constantly on the lowlevel (reference voltage Vss) except when at least the start signal Dstor the output signal OUTk−1 of the preceding stage once rises to thehigh level. Therefore, the period in which the gate voltage of each TFT1 is positive relatively with respect to any lower voltage of the drainvoltage and the source voltage is only a period in which the clocksignal CK1 or CK2 is once on the high level if the clock signals CK1 andCK2, the start signal Dst and the reset signal Dend are equal to eachother, the high level voltage is equal to the power supply voltage Vddand the low level voltage is equal to the reference voltage Vss.

Further, when the high level voltage of the clock signals CK1 and CK2,the start signal Dst and the reset signal Dend is a voltage attenuatedby a parasitic capacitance between the gate and the drain of the TFT 1,for example, it is lower than the potential of the node A3 in the periodfrom the timing T3 to the timing T4, the gate voltage of the TFT 1 isconstantly lower than the source voltage and the drain voltage of theTFT. It is, therefore, possible to suppress shift of the gate thresholdvoltage of the TFT 1 of the k-th stage RS(k) to be positive.

As described above, in the shift register constituting the gate driver152 in this embodiment, the period in which the gate voltage of the TFT1 of each stage is positive relatively with respect to the drain andsource voltages is short. In connection with the characteristic of theTFT, when the gate voltage becomes positive relatively with respect tothe drain and source voltages, the threshold value characteristic is aptto shift to be positive. However, even if the gate voltage becomesnegative relatively with respect to the drain and source voltages, thethreshold characteristic hardly shift to be negative.

In other words, since the characteristic of the TFT 1 rarely changeseven if the shift register of this embodiment is used for a long time,there hardly occurs the case that the TFT 1 is not turned on with thetiming at which the TFT 1 should be essentially turned on and theelectric charge can not be accumulated in the nodes A1 to An. Therefore,the shift register can stably operate for a long period of time, therebyimproving the durability.

Further, a failure of the display portion 210 in which the shiftregister is applied as the gate driver 152 is of course eliminated,which improves the durability of the digital still camera including thisportion.

In this embodiment, the gate driver 152 applied to the liquid crystaldisplay constituting the display portion 210 has a structure shown inFIG. 11, and is configured by the shift register which operates inaccordance with the timing chart shown in FIG. 12 by the control signaloutputted from the controller 150. However, the shift registerapplicable as the above-described gate driver 152 is not restrictedthereto.

FIG. 13 is a view showing the circuit structure of another shiftregister applicable as the gate driver 152, the top gate driver 72 andthe bottom gate driver 73. Giving description as to a difference fromthe shift register shown in FIG. 11, the clock signal CK1 is supplied tothe drain of the TFT 1 in the odd-numbered stages RS(1), RS(3), . . . ,RS(n−1), and the clock signal CK2 is supplied to the same in theeven-numbered stages RS(2), RS(4), . . . , RS(n), respectively. The highlevel voltage of the clock signals CK1 and CK2, the start signal Dst andthe reset signal Dend is equal to the power supply voltage Vdd, and thelow level voltage of the same is equal to the reference voltage Vss.

A difference in operation of the shift register shown in FIG. 13 fromthe shift register illustrated in FIG. 11 will now be described withreference to the timing chart of FIG. 14. In a period from the timing T0to another timing T1, when the start signal Dst rises to the high leveland the TFT1 of the first stage RS(1) is turned on, the clock signal CK2supplied to the drain of the TFT 1 rises to the high level, therebyaccumulating the electric charge in the node A1.

In a period from the timing T1 to the next timing T2, when the outputsignal OUT1 of the first stage RS(1) rises to the high level and the TFT1 of the second stage RS(2) is turned on, the clock signal CK1 suppliedto the drain of the TFT 1 changes to the high level, thus accumulatingthe electric charge in the node A2. Thereafter, in a period from thetiming Tn−1 to the timing Tn, when the output signal OUTn−1 of then−1-th stage RS(n−1) rises to the high level and the TFT 1 of the n-thstage RS(n) is turned on, the clock signal CK2 fed to the drain of theTFT 1 similarly changes to the high level and the electric charge isaccumulated in the node An.

As indicated by the lower three sections in FIG. 14, explaining a changein potential level of the gate, the drain and the source of the TFT 1 inthis shift register by taking the third stage RS(3) for instance, onlywhen the output signal OUT2 of the second stage RS(2) is on the highlevel in the period from the timing T2 to the timing T3, the potentialis on the high level (substantially Vdd). The drain voltage is on thehigh level (substantially vdd) only when the clock signal CK2 is on thehigh level. When the electric charge is accumulated in the node A3 inthe timing T2, the source voltage changes to a voltage level which islower than Vdd by its threshold voltage. Further, while the clock signalCK1 is on the high level in a period from the timing T3 to the timingT4, the source voltage changes to a level which is approximately twofoldof the power supply voltage Vdd.

Here, if the period in which the drain voltage of the TFT 1 is higherthan the gate voltage is sufficiently long, the gate threshold voltageis shifted to be negative, and the potential of the node A is increasedby the leak electric current in the OFF state, which may possiblyprovoke a malfunction. However, in this shift register, the period inwhich the drain voltage of the TFT 1 is on the high level is shorterthan that of the shift register illustrated in FIG. 11. That is, theperiod in which a difference in potential between the gate and the drainand between the source and the drain of the TFT 1 is short. Therefore,the voltage stress applied to the TFT 1 is smaller than that in theshift register depicted in FIG. 11, and the leak electric current isalso small. Moreover, the device characteristic of the TFT 1 is hardlydeteriorated, and hence a failure is hardly produced even if the shiftregister is used for a long time.

FIG. 15 is a view showing the circuit structure of still another shiftregister applicable as the gate driver 152, the top gate driver 72 andthe bottom gate driver 73. Giving description as to a difference fromthe shift register shown in FIG. 11, a voltage signal V1 is supplied.The high level of the voltage signal V1 is lower the level of the powersupply voltage Vdd, but it is a level capable of accumulating in thenodes A1 to An the electric charge which is sufficient for turning onthe TFTs 2 and 5. On the other hand, the low level of the voltage signalV1 is the same as the reference voltage Vss. The high level voltage ofthe clock signals CK1 and CK2, the start signal Dst and the reset signalDend is equal to the power supply voltage Vdd, and the low level voltageof the same is equal to the reference voltage Vss.

A difference in operation of the shift register shown in FIG. 15 fromthe shift register depicted in FIG. 11 will now be described withreference to the timing chart in FIG. 16. In the operation according tothis timing chart, the voltage signal V1 is constantly maintained on thehigh level.

In a period from the timing T0 to another timing T1, when the startsignal Dst changes to the high level and the TFT 1 of the first stageRS(1) is turned on, the voltage signal V1 is outputting from the drainof the TFT 1 to the source, thereby accumulating the electric charge inthe node A1. At this time, although the potential of the node A1 islower than that of the voltage signal V1, which is lower than the powersupply voltage Vdd, by the threshold voltage of the TFT 1, it is higherthan the threshold voltage of the TFTs 2 and 5. As a result, the TFTs 2and 5 are turned on and the TFT 3 is turned off in the first stageRS(1). Further, in the timing T1, when the clock signal CK1 rises, thelevel of the output signal OUT1 becomes the high level.

Thereafter, in a period from the timing Tn−1 to the timing Tn, theoutput signal OUTn−1 of the n−1-th stage RS(n−1) rises to the high leveland the TFT 1 of the n-th stage RS(n) is turned on similarly.Consequently, the electric charge capable of providing the potentiallower than the voltage signal V1 by the threshold voltage of the TFT 1is accumulated in the node An, and the TFTs 2 and 5 are turned on andthe TFT 3 is turned off in the n-th stage RS(n). Furthermore, in thetiming Tn, when the clock signal CK2 rises, the level of the outputsignal OUTn becomes the high level.

Description will now be given as to how the potential of the gate, thedrain and the source of one TFT 1 changes in this shift register bytaking the TFT 1 in the third stage RS(3) for instance with reference tothe lower three sections in FIG. 16. AS shown in the drawing, the gatevoltage of the TFT 1 is substantially equal to the power supply voltageVdd only when the output signal OUT2 of the second stage RS(2) is on thehigh level in a period from the timing T2 to the timing T3.

The drain voltage of the TFT 1 is maintained on a level of the voltagesignal V1, namely, a level which is slightly lower than the power supplyvoltage Vdd. When the electric charge is accumulated in the node A3 inthe timing T2, the source voltage of the TFT 1 changes to the voltagelevel lower than the voltage signal V1 by its threshold voltage.Moreover, this source voltage changes to the level higher than thevoltage signal V1 by nearly the power supply voltage Vdd, when the clocksignal CK1 is on the high level in a period from the timing T3 to thetiming T4.

That is, the level of the source voltage of the TFT 1 at this time isslightly higher than the power supply voltage Vdd but sufficiently lowerthan a voltage which is twofold of the power supply voltage Vdd.Therefore, in the TFT 1, a difference in potential between the gate andthe drain when the gate is on the OFF level becomes smaller, and adifference in potential between the gate and the source when the sourcevoltage is maximum also becomes smaller. Similarly, the gate voltage ofthe TFT 2, the gate voltage of the TFT 5, and the drain voltage of theTFT 6 do not become large as those in the shift register shown in FIG.11. Thus, the large voltage stress is not applied to the TFTs 1, 2, 5and 6, and the device characteristic of the TFT 1, 2, 5 and 6 is hardlydeteriorated as compared with the shift register depicted in FIG. 11.Therefore, a failure hardly occurs even if the shift register is usedfor a long time.

The shift register shown in FIG. 15 can also operate in accordance withthe timing chart illustrated in FIG. 17. In the operation according tothis timing chart, the voltage signal V1 changes to the high level onlyin a period in which either the clock signal CK1 or CK2 is on the highlevel. Description will be given as to a difference of the operationaccording to this timing chart from the operation according to thetiming chart depicted in FIG. 16.

Only when the start signal Dst is on the high level in a period from thetiming T0 to another timing T1, the voltage signal V1 rises to the highlevel, and the electric charge is accumulated in the node A1. Only whenthe output signal OUT1 is on the high level in a period from the timingT1 to another timing T2, the voltage signal V1 changes to the highlevel, and the electric charge is accumulated in the node A2.Thereafter, in a period from the timing Tn−1 to the timing Tn, only whenthe output signal OUTn−1 is on the high level, the voltage signal V1similarly rises to the high level, thereby accumulating the electriccharge in the node An.

In case of this operation, as shown in the lower three sections in FIG.17 by taking the third stage RS(1) for instance, a period in which adifference in potential between the gate and the drain and between thesource and the drain of the TFT 1 is shorter than that in case of theoperation illustrated in FIG. 16, and the voltage stress applied to theTFT 1 is small. Therefore, since the device characteristic of the TFT 1is hardly deteriorated as compared with the case of the operation shownin FIG. 16, a failure hardly occurs even if the shift register is usedfor a long time.

FIG. 18 is a view showing the circuit structure of shift registersapplicable as the gate driver 152, the top gate driver 72 and the bottomgate driver 73. Explaining a difference from the shift registerillustrated in FIG. 13, a clock signal CK1′ is supplied to the drain ofthe TFT 1 in the odd-numbered stages RS(1), RS(3), . . . , RS(n−1), anda clock signal CK2′ is supplied to the same in the even-numbered stagesRS(2), RS(4), . . . , RS(n), respectively. The high level of the clocksignals CK1′ and CK2′ is lower than the level of the power supplyvoltage Vdd but it can accumulate in the nodes A1 to An the electriccharge which is sufficient for turning on the TFTs 2 and 5.

A difference in operation of the shift register shown in FIG. 18 fromthe shift register depicted in FIG. 13 will now be described withreference to the timing chart in FIG. 19. When the start signal Dstchanges to the high level in a period from the timing T0 to the timingT1, the clock signal CK2′ rises to the high level, and the electriccharge is accumulated in the node A1. When the output signal OUT1changes to the high level in a period from the timing T1 to the timingT2, the clock signal CK1′ rises to the high level, and the electriccharge is accumulated in the node A2. Thereafter, when the output signalOUTn−1 rises to the high level in a period from the timing Tn−1 to thetiming Tn, the clock signal CK1′ rises to the high level and theelectric charge is accumulated in the node An.

As shown in the lower three sections in FIG. 19 by taking the TFT 1 ofthe third stage RS(3) for instance, the source voltage of each TFT 1 isslightly higher than the power supply voltage Vdd even when the sourcevoltage is on the maximum level, but it is sufficiently lower than avoltage which is twofold of the power supply voltage Vdd. Similarly, thegate voltage of the TFT 2, the gate voltage of the TFT 5 and the drainvoltage of the TFT 6 do not become as large as those of the shiftregister shown in FIG. 13. Accordingly, the large voltage stress is notapplied to the TFTs 1, 2, 5 and 6. Moreover, a period in which adifference in potential between the gate and the drain and between thesource and the drain of the TFT 1 is generated is shorter than that inthe shift register shown in FIG. 15. Since the device characteristic ofthe TFTs 1, 2, 5 and 6 is hardly deteriorated as compared with the shiftregisters shown in FIGS. 13 and 15, a failure is hardly produced even ifthe shift register is used for a long time.

Second Embodiment

A digital still camera according to this embodiment is substantially thesame as that according to the first embodiment but different from theforegoing embodiment in that an angle sensor 240 indicated by a dottedline in FIG. 2 is provided. In addition, a sift register applied as thegate driver 152 in the display portion 210 is different from the firstembodiment, and a shift register which can shift an output signal inboth forward and backward directions is used in this embodiment.Additionally, in this regard, signals outputted as the control signalgroup Gcnt from the controller 150 are also different slightly.

The angle sensor 240 detects an angle of a lens unit portion 202 withrespect to a camera main body portion 201. A detection signal of theangle sensor 240 is inputted to a CPU 222, and the CPU 222 supplies to adisplay portion 210 a control signal which indicates that a displayscanning direction (shift operation direction of the shift registerapplied as the gate driver 152) is either the forward direction or thebackward direction in accordance with this detection signal.

FIG. 20 is a view showing a circuit configuration of the shift registerapplied as the gate driver 152 in this embodiment. This shift registeris also constituted by n stages RS(1) to RS(n) whose number is equal tothat of gate lines GL in a display area 151, and each of the stagesRS(1) to RS(n) is composed of six TFTs 1 to 6 as similar to the shiftregister illustrated in FIG. 11. Here, the TFTs 1 to 6 are all likewisen channel type field effect transistors.

Giving description on a difference of the shift register shown in FIG.20 from that illustrated in FIG. 11, a voltage signal V1 is supplied tothe drain of the TFT 1 in each of the stages RS(1) to RS(n) instead ofthe power supply voltage vdd. A voltage signal V2 is supplied to thesource of the TFT 6 in each of the stages RS(1) to RS(n) in place of thereference voltage Vss.

A control signal D1 is fed to the gate of the TFT 1 in the first stageRS(1) instead of the start signal Dst. A control signal D2 is suppliedto the gate of the TFT 6 in the n-th stage RS(n) in place of the resetsignal Dend. Levels of the voltage signals V1 and V2 differ depending onthe forward operation and the backward operation, and the timing inwhich the control signals D1 and D2 rise to the high level differdepending on the forward operation and the backward operation.

The operation of the digital still camera according to this embodimentwill now be described. Explanation will be first given as to theoperation of the shift register constituting the above-mentioned gatedriver 152 in accordance with the case of forward shift and the case ofbackward shift with reference to the timing charts of FIGS. 21 and 22.

It is to be noted that the high level of the clock signals CK1 and CK2,the voltage signals V1 and V2, and the control signals D1 and D2 isequal to the power supply voltage Vdd in these timing charts. On theother hand, the low level of these signals is equal to the referencevoltage Vss. One scanning period Q corresponds to one horizontal periodin the display portion 210.

Further, before starting the shift operation according to these timingcharts (before T0), all of the output signals OUT1 to OUTn are on thelow level. Further, in any of the stages RS(1) to RS(n), no electriccharge is accumulated in the nodes A1 to An, and the TFTs 2 and 5 are inthe ON state while the TFT 3 is in the OFF state.

FIG. 21 is a timing chart showing the operation in case of the forwardshift. In this case, the level of the voltage signal V1 is maintained onthe high level equal to the power supply voltage Vdd, and the level ofthe voltage signal V2 is maintained on the low level equal to thereference voltage Vss. Furthermore, the control signal D1 rises to thehigh level only in a fixed period from the timing T0 to the timing T1.The control signal D2 rises to the high level only in a fixed periodfrom the timing Tn to the timing Tn+1.

That is, in the first embodiment, when the control signal D1 and thecontrol signal D2 are replaced with the start signal Dst and the resetsignal Dend, respectively, the operation equal to that of the shiftregister explained in conjunction with the timing chart of FIG. 12 canbe obtained. Therefore, the output signals OUT1 to OUTn sequentiallyrise to the high level and are shifted for each fixed period in onescanning period Q.

On the other hand, FIG. 22 is a timing chart showing the operation incase of the backward shift. In this case, the level of the voltagesignal V1 is maintained on the low level equal to the reference voltageVss, and the level of the voltage signal V2 is maintained on the highlevel equal to the power supply voltage Vdd. Further, the control signalD2 rises to the high level only in a fixed period from the timing T0 tothe timing T1. The control signal D1 rises to the high level only in afixed period from the timing Tn to the timing Tn+1.

In a period from the timing T0 to the timing T1, when the control signalD2 rises to the high level, the TFT 6 of the n-th stage RS(n) is turnedon, and the voltage signal V2 on the high level is outputted from thesource of the TFT 6 to the source. As a result, the electric charge isaccumulated in the node An of the n-th stage RS(n), and the TFTs 2 and 5are turned on while the TFT 3 is turned off. Since the TFT 2 of the n-thstage RS(n) is turned on but the clock signal CK2 remains on the lowlevel in this period, the output signal OUT2 remains on the low level.

Subsequently, in the timing T1, when the clock signal CK2 rises to thehigh level, this signal is outputted from the drain of the TFT 2 of then-th stage RS(n) to the source, and the output signal OUTn rises to thehigh level. Thereafter, when the clock signal CK2 falls until the timingT2, the output signal OUTn changes to the low level.

Furthermore, in a period from the timing T1 to the timing T2, the TFT 6of the n−1-th stage RS(n−1) is turned on by the output signal OUTn ofthe n-th stage RS(n) which has risen to the high level. Consequently,outputting the voltage signal V2 on the high level from the drain of theTFT 6 in the n−1-th stage RS(n−1) causes the potential of the node An−1to change to the high level, and the TFTs 2 and 5 are turned on whilethe TFT 3 is turned off in the n−1-th stage RS(n−1).

Then, in the next timing T2, when the clock signal CK1 changes to thehigh level, this signal is outputted from the drain of the TFT2 of then−1-th stage RS(n−1) to the source, and the level of the output signalOUTn−1 varies to the high level. As a result, the TFT 1 is now turned onin the n-th stage RS(n), and the electric charge accumulated in the nodeAn is discharged, and the TFTs 2 and 5 are turned off while the TFT 3 isturned on in the n-th stage RS(n). Thereafter, when the clock signal CK1falls until the timing T3, the output signal OUTn−1 falls to the lowlevel.

Furthermore, in a period from the timing T1 to another timing T2, theTFT 6 of the n−2-th stage RS(n−2) is turned on by the output signalOUTn−1 of the n−1-th stage RS(n−1) which has risen to the high level.Consequently, when the voltage signal V2 on the high level is outputtedfrom the drain of the TFT 6 in the n−2-th stage RS(n−2), the potentialof the node An−2 rises to the high level, and the TFTs 2 and 5 areturned on while the TFT 3 is turned off in the n−2-th stage RS(n−2).

Thereafter, the n−2-th and preceding stages RS(n−2), RS(n−3), . . .repeat the operation similar to the above in accordance with each onescanning period Q toward the preceding stages, and the output signalsOUTn−2, OUTn−3, . . . hence change to the high level in eachpredetermined period within one scanning period Q. Moreover, in a periodfrom the timing Tn−1 to the timing Tn, the TFT 6 of the first stageRS(1) is turned on by the output signal OUT2 of the second stage RS(2)which has risen to the high level. Consequently, the electric charge isaccumulated in the node A1 of the first stage RS(1), and the TFTs 2 and5 are turned on while the TFT 3 is turned off.

Then, in the timing Tn, when the clock signal CK1 changes to the highlevel, this signal is outputted from the drain of the TFT 2 of the firststage RS(1) to the source, the level of the output signal OUT1 varies tothe high level. Thereafter, when the clock signal CK1 falls until thetiming Tn+1, the output signal OUT1 changes to the low level.

Subsequently, in the timing Tn+1, the level of the control signal D1changes to the high level. As a result, the TFT 1 of the first stageRS(1) is turned on, which discharges the electric charge accumulated inthe node A1, thereby turning off the TFTs 2 and 5 and turning on the TFT3 in the second stage RS(2). Moreover, before the control signal D2changes to the high level, no electric charge is accumulated in thenodes A1 to An in all of the stages RS(1) to RS(n), thus maintaining theTFTs 2 and 5 in the ON stage and the TFT 3 in the OFF state.

The operation of the entire digital still camera according to thisembodiment will now be described, but this is the same as the firstembodiment except the following point. Explaining a difference from thefirst embodiment, the angle sensor 240 detects an angle of the lensuntil portion 202 with respect to the camera main body portion 201 andinputs the detection signal to the CPU 222. The CPU 222 then supplies tothe display portion 210 a control signal according to the receiveddetection signal.

In the display portion 210, the controller 150 switches the controlsignals D1 and D2 and the voltage signals V1 and V2 supplied as thecontrol signal group Gcnt to the gate driver 152 so that the forwardshift can be effected, when the control signal indicating that theimaging lens 202a of the lens unit 202 is provided on the opposite sideof the display portion 210 is supplied from the CPU 222. When thecontrol signal indicating that the imaging lens 202a is provided on thedisplay portion 210 side is supplied from the CPU 222, the controller150 switches the control signals D1 and D2 and the voltage signals V1and V2 fed as the control signal group Gcnt to the gate driver 152 sothat the backward shift can be performed.

Description will now be given as to the operation when an image ispicked up by the digital still camera according to this embodiment,especially the relationship between the direction of the lens unitportion 202 and an image displayed in the display portion 210 by givinga specific example. Here, it is assumed that the mode setting key 212ais set in the recording mode and the CPU 222 supplies to the displayportion 210 a control signal for changing a scanning direction (shiftdirection of the shift register constituting the gate driver 152) of thedisplay area 151 in accordance with a detection signal of the anglesensor 240.

As shown in FIG. 23A, description will be first give on the operation ofthe digital still camera when picking up an image of an object whichexists in front of a camera operator. In this case, the camera operatorswivels the imaging lens 202a of the lens unit portion 202 in such amanner that it is situated on the same side as the display portion 210of the camera main body portion 201, namely, the lens unit portion 202is positioned at substantially 0° with respect to the camera main bodyportion 201 and picks up an image. At this time, the scanning directionof the display area 151 by the gate driver 152 is the forward direction.

In this state, as shown in FIG. 23A, the arrangement of the pixels P(1,1) to P(n, m) in the display area 151 matches with the original verticaland horizontal directions of the display area 151. Further, the verticaland horizontal directions of the lens unit portion 202 matches with theoriginal vertical and horizontal direction of an image. At this time,horizontal scanning from the left to the right and vertical scanningfrom the top to the bottom in FIG. 23A in accordance with the imageformed by the imaging lens 202a cause an electrical signal to beoutputted from each pixel of the CCD imaging device 220, and thecorresponding image data is developed in the VRAM area of the RAM 224.

On the other hand, in the display portion 210, the developed image datais fetched in accordance with a direction indicted by a horizontal arrowshown in FIG. 23B and outputted to the first to m-th drain lines DL inthe display area 151 within one horizontal period. Furthermore, the gatedriver 152 sequentially selects the gate lines GL in the order from thefirst to the n-th gate lines (order from the top line to the lower linesin FIG. 23B) in the display area 151.

As a result, the image data corresponding to the signal outputted fromthe pixel which is originally provided on the top in the CCD imagingdevice 220 is displayed on the essentially upper pixel in the displayarea 151 (upper side in FIG. 23B), and the image data corresponding tothe signal outputted from the pixel which is originally provided on theleft side in the CCD imaging device 220 is displayed on the essentiallyleft pixel (left side in FIG. 23B) in the display area 151. Therefore,as shown in FIG. 23B, an image whose direction is equal to that of thepicked-up image.

Subsequently, as shown in FIG. 24A, description will now be given as tothe operation of the digital still camera when an object is provided onthe display portion 210 side, for example, when a camera operatorhim/herself is an object. In this case, the camera operator swivels theimaging lens 202a of the lens unit portion 202 in such a manner thatthis lens comes to the opposite side of the display portion 210 of thecamera main body portion 201, namely he/she swivels the lens unitportion 202 so as to be positioned at substantially 180° with respect tothe camera main body portion 201 in order to pick up an image. At thistime, the scanning direction of the display area 151 by the gate driver152 is the backward direction.

In this state, as shown in FIG. 24A, the arrangement of the pixels P(1,1) to P(n, m) in the display area 151 is opposite to the originalvertical and horizontal directions of the display area 151. Moreover,the vertical and horizontal directions of the lens unit portion 202match with the vertical and horizontal directions of an image. At thistime, horizontal scanning from the right and left and vertical scanningfrom the top to the bottom in FIG. 24A cause an electrical signal to beoutputted from each pixel of the CCD imaging device 220, and thecorresponding image data is developed in the VRAM area of the RAM 224.

On the other hand, in the display portion 210, the developed image datais fetched in accordance with the direction indicated by a horizontalarrow shown in FIG. 24B and outputted to the first to the m-th drainliens DL in the display area 151 within one horizontal period. Inaddition, the gate driver 152 sequentially selects the gate lines GL inthe order from the first to the n-th gate lines (order from the lowestgate line to the upper gate lines in FIG. 24B) in the display area 151.

Consequently, the image data corresponding to the signal outputted fromthe pixel which is originally provided on the top in the CCD imagingdevice 220 is displayed on the essentially lower pixel (lower side inFIG. 24B) in the display area 151, and the image data corresponding tothe signal outputted from the pixel which is originally provided on theleft in the CCD imaging device 220 is displayed on the essentially rightpixel (right side in FIG. 24B) in the display area 151. Therefore, asshown in FIG. 24B, a mirror of the picked-up image is displayed.

As described above, in the shift register applied as the gate driver 152in the digital still camera according to this embodiment, the TFT 1functions as a transistor for accumulating the electric charge in thenodes A1 to An and the TFT 6 serves as a transistor for discharging theaccumulated electric charge in case of the forward operation. On theother hand, in case of the backward operation, the TFT 1 functions as atransistor for discharging the electric charge accumulated in the nodesA1 to An and the TFT 6 acts as a transistor for accumulating theelectric charge.

Since the TFTs 1 and 6 can have such functions, a number of the TFTs 1to 6 constituting the respective stages RS(1) to RS(n) can be equal tothat in the shift registers applied as the gate driver 152 in the firstembodiment. Therefore, an area can not be increased as compared withthat in the first embodiment, and the relative area of the image displayregion can not be small even if the gate driver 152 is formed on thesame substrate as that of the display area 151.

In addition, by applying the shift register capable of performing shiftoperation in both the forward direction and the backward direction tothe gate driver 152, a mirror image of an image picked up by the CCDimaging device 220 can be displayed on the display portion 210 by onlycontrolling the control signal group Gcnt supplied to the controller 150to the gate driver 152. That is, in the digital still camera accordingto this embodiment, the mirror image can be displayed on the displayportion 210 without executing the complicated control for reading theimage data developed in the VRAM area.

In this embodiment, the gate driver 152 has the structure shown in FIG.20 and is constituted by the shift register which operates in accordancewith the timing chart shown in FIG. 21 or 22 by the control signaloutputted from the controller 150. In this embodiment, however, themethod for driving the shift register applicable as the gate driver 152is not restricted thereto, and the structure of the shift register isnot limited thereto.

FIGS. 25 and 26 are timing charts showing another operation of the shiftregister illustrated in FIG. 20. In case of the forward operation, asshown in FIG. 25, the voltage signal V2 is maintained on the low levelas similar to the case in FIG. 21, but the voltage signal V1 rises tothe high level only when the clock signal CK1 or CK2 is on the highlevel. For example, in the period from the timing T0 to T1, when thecontrol signal D1 changes to the high level, the clock signal CK1 alsorises to the high level so that the TFT 1 is turned on in the firststage RS(1), thereby accumulating the electric charge in the node A1.

On the other hand, in case of the backward operation, as shown in FIG.26, the voltage signal V1 is maintained on the low level as similar tothe case in FIG. 22, but the voltage signal V2 rises to the high levelonly when the clock signal CK1 or CK2 is on the high level. For example,in the period from the timing T0 to the timing T1, when the controlsignal D2 changes to the high level, the clock signal CK2 also rises tothe high level, and the TFT 1 is turned on in the n-th stage RS(n),thereby accumulating the electric charge in the node An.

In these cases, the period in which a difference in potential betweenthe gate and the drain and between the source and the drain of each ofthe TFTs 1 and 6 becomes shorter than that in case of operating inaccordance with the timing charts shown in FIGS. 21 and 22. As a result,the voltage stress applied to the TFTs 1 and 6 can be reduced, and thecharacteristic is hardly deteriorated, thereby resisting use for a longtime.

FIG. 27 is a view showing a circuit structure of a further shiftregister applicable as the gate driver 152 in this embodiment. Givingdescription as to a difference from the shift register shown in FIG. 20,the voltage signal V2 is supplied to the drain of the TFT 1 and thevoltage signal V1 is supplied to the source of the TFT 6 in theodd-numbered stages RS(1), RS(3), . . . , RS(n−1). The voltage signal V1is supplied to the drain of the TFT 1 and the voltage signal V2 is fedto the source of the TFT 6 in the even-numbered stages RS(2), RS(4), . .. , RS(n).

The operation of the shift register shown in FIG. 27 will now bedescribed with reference to the timing charts in FIGS. 28 and 29. Incase of the forward operation, in a period from the timing T0 to thetiming T1, when the control signal D1 rises to the high level, the TFT 1of the first stage RS(1) is turned on, and the electric charge isaccumulated in the node A1 by the voltage signal V2 which has risen tothe high level. In a period from the timing T1 to the timing T2, whenthe clock signal CK1 changes to the high level, the output signal OUT1of the first stage RS(1) rises to the high level. This turns on the TFT1 of the second stage RS(2), and the electric charge is accumulated inthe node A2 by the voltage signal V1 which has risen to the high level.

In a next period from the timing T2 to the timing T3, when the clocksignal CK2 changes to the high level, the output signal OUT2 of thesecond stage RS(2) rises to the high level. This turns on the TFT 1 ofthe third stage RS(3), and the electric charge is accumulated in thenode A3 by the voltage signal V2 which has risen to the high level.Additionally, the TFT 6 of the first stage RS(1) is turned on by theoutput signal OUT2 which has risen to the high level. At this time,since the voltage signal V1 is on the low level, the electric chargeaccumulated in the node A1 is discharged.

Thereafter, similarly, in a period from the timing Tn to the timingTn+1, when the clock signal CK2 changes to the high level, the outputsignal OUTn of the n-th stage RS(n) rises to the high level.Consequently, the TFT 6 of the n−1-th stage RS(n−1) is turned on.Further, since the voltage signal V1 is on the low level, the electriccharge accumulated in the node An−1 is discharged. Then, in the timingTn+1, the control signal D2 varies to the high level, and the TFT6 ofthe n-th stage RS(n) is turned on. At this time, since the voltagesignal V2 is on the low level, the electric charge accumulated in thenode An is discharged.

On the other hand, in case of the backward operation, in the period fromthe timing T0 to the timing T1, when the control signal D2 rises to thehigh level, the TFT 6 of the n-th stage RS(n) is turned on, and theelectric charge is accumulated in the node An by the voltage signal V2which has risen to the high level. In the period from the timing T1 tothe timing T2, when the clock signal CK2 changes to the high level, theoutput signal OUTn of the n-th stage RS(n) rises to the high level. As aresult, the TFT 6 of the n−1-th stage RS(n−1) is turned on, and theelectric charge is accumulated in the node An−1 by the voltage signal V2which has risen to the high level.

In the next period from the timing T2 to the timing T3, when the clocksignal CK1 changes to the high level, the output signal OUTn−1 of then−1-th stage RS(n−1) rises to the high level. Consequently, the TFT 1 ofthe n-th stage RS(n) is turned on, and the voltage signal V1 is on thelow level, thereby discharging the electric charge accumulated in thenode An.

Thereafter, similarly, in the period from the timing Tn to the timingTn+1, when the clock signal CK1 changes to the high level, the outputsignal OUT1 of the first stage RS(1) rises to the high level. As aresult, the TFT 1 of the second stage RS(2) is turned on, and thevoltage signal V1 is on the low level, thereby discharging the electriccharge accumulated in the node A2. Then, in the timing Tn+1, the controlsignal D1 varies to the high level, and the TFT 1 of the first stageRS(1) is turned on. At this time, since the voltage signal V2 is on thelow level, the electric charge accumulated in the node A1 is discharged.

FIG. 30 is a view showing a circuit structure of a still further shiftregister applicable as the gate driver 152 in this embodiment. Givingdescription as to a difference from the shift register illustrated inFIG. 20, the voltage signal is supplied to the drain of the TFT 1 andthe voltage signal V4 is fed to the source of the TFT 6 in theodd-numbered stages RS(1), RS(3), . . . , RS(n−1). In the even-numberedstages RS(2), RS(4), . . . , RS(n), the voltage signal V1 is supplied tothe drain of the TFT 1, and the voltage signal V3 is supplied to thesource of the TFT 6.

The operation of the shift register shown in FIG. 30 will now beexplained with reference to the timing charts of FIGS. 31 and 32. If thevoltage signal fed to the source of the TFT 6 in the odd-numbered stagesRS(1), RS(3), . . . , RS(n−1) is substituted by V4 and the voltagesignal fed to the source of the TFT 6 in the even-numbered stages RS(2),RS(4), . . . , RS(n) is substituted by V3, the operation of this shiftregister is substantially the same as that of the shift registerillustrated in FIG. 27.

In case of the forward operation shown in FIG. 31, however, the sourcevoltage (voltages signals V3 and V4) of the TFT 6 in each of the stagesRS(1) to RS(n) is maintained on the low level. Furthermore, in case ofthe backward operation shown in FIG. 32, the drain voltage (voltagesignals V1 and V2) of the TFT 1 of each of the stages RS(1) to RS(n) ismaintained on the low level. That is, in regard to the TFT 1 in theforward operation and the TFT 6 in the backward operation, a period inwhich a difference in potential is produced between the gate and thedrain and the source of the drain is short. Thus, since the voltagestress applied to the TFTs 1 and 6 can be reduced, the devicecharacteristic of the TFTs 1 and 6 is hardly deteriorated, and a failureis unlikely to occur even in use for a long time.

In each shift register described in this embodiment, the high level ofthe voltage signals V1 to V4 supplied to the drain of the TFT 1 or thesource of the TFT 6 may be lower than the power supply voltage Vdd if itis a voltage level which can successfully turn on the TFTs 2 and 5 bythe electric charge accumulated in the nodes A1 to An. Therefore, thevoltage stress applied to the TFTs 1 and 6 as well as the TFTs 2 and 5can be smaller than that in case of operating the shift register inaccordance with each of the above-mentioned timing charts.

The long normal operation is enabled by setting respective values (W/L)of the TFT 1, the TFT 2, the TFT 3, the TFT 4, the TFT 5 and the TFT 6as values (W/L) of the TFT 21, the TFT 25, the TFT 26, the TFT 23, theTFT 22 and the TFT 24 shown in Tables 1 and 2.

Other Embodiments

The present invention is not restricted to the above-described first andsecond embodiments, and various modifications and applications of thisinvention are possible. Other embodiments to which the present inventionis applied will be described hereinafter.

In the second embodiment, the direction of the shift operation by theshift register applied as the gate driver 152, namely, the forwarddirection or the backward direction is automatically set in accordancewith an angle of the lens unit portion 202 with respect to the cameramain body portion 201 detected by the angle sensor 240. Selection of theforward operation or the backward operation may be, however, determinedby a user manipulating keys of the key input portion 212.

The example where the shift register illustrated in FIGS. 11, 13, 15,18, 20, 27 and 30 is applied as the gate driver 152 of the liquidcrystal display has been described. However, the shift register may beused as a driver for selecting lines in a display unit other than theliquid crystal display, for example, a plasma display, a field emissiondisplay, an organic EL display. Moreover, such a shift register may bealso used as a driver for driving an imaging device having imagingpixels being aligned in a predetermined arrangement (for example, amatrix arrangement) as shown in FIG. 10.

The shift register shown in FIGS. 11, 13, 15, 18, 20, 27 and 30 may beapplied to any use other than that as a driver for driving an imagingdevice or a display device. For example, such a shift register can bealso applied to the case where serial data is converted into paralleldata in a data processor and the like.

The TFTs 1 to 6 constituting the shift register described in the firstand second embodiments are all of the n channel type. On the other hand,the p channel type TFTs can be also used. For example, when the TFTswhich are all of the p channel type are used, inverting the high and lowlevels of each signal from those of the n channel type TFTs can suffice.

In the first and second embodiments, although description has been givenas to the example where the present invention is applied to the digitalstill camera for picking up a still image, the present invention can bealso applied to a video camera using a liquid crystal display and thelike for a finder for picking up a moving image and visually confirmingan image which is in the shooting process. When the direction of theliquid crystal display can swivel with respect to the imaging lens inthe video camera, the shift register described in the second embodimentcan be used as the gate driver for the liquid crystal display to displayan mirror image.

As described above, in the shift register according to the presentinvention, fluctuations in the characteristic of the first or secondtransistor is reduced, and the stable operation is enabled for a longtime.

Further, by adjusting the high level of the first and second voltagesignals and its period, a failure of the first and second transistorhardly occurs, thereby enabling the stable operation for a long time.

Furthermore, when accumulation of the electric charge in the wiring ofeither the first or second transistor and discharge of the accumulatedelectric charge can be switched, the shift operation in both the forwarddirection and the backward direction is enabled.

Moreover, an electronic apparatus in which the shift register accordingto the present invention is applied as the driver can be superior in thedurability.

In addition, by applying the shift register capable of performing theshift operation in the both forward and backward directions as thedriver, an image whose vertical direction is inverted can be readilydisplayed.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A shift register comprising a plurality of stages electricallyconnected to each other, each of said stages comprising: a firsttransistor having a first control terminal, which is turned on by asignal on a predetermined level supplied from one stage to said firstcontrol terminal, and outputs said signal on a predetermined level fromone end of a first electric current path to the other end of said firstelectric current path; a second transistor having a second controlterminal, which is turned on in accordance with a voltage applied to awiring between said second control terminal and the other end of saidfirst electric current path of said first transistor, and outputs afirst or second signal supplied from outside to one end of a secondelectric current path as an output signal from the other end of saidsecond electric current path; a load for outputting a power supplyvoltage supplied from outside; a third transistor having a third controlterminal, which is turned on in accordance with a voltage applied to awiring between said third control terminal and the other end of saidfirst electric current path of said first transistor, and outputs saidpower supply voltage, which is fed from outside through said load, fromone end of a third electric current path to the other end of said thirdelectric current path so that said power supply voltage outputted fromsaid load is displaced to a voltage on a predetermined level; and afourth transistor having a fourth control terminal, which is turned onin accordance with a voltage applied to a wiring between said fourthcontrol terminal and said load, has one end of a fourth electric currentpath, connected to the other end of said second electric current path ofsaid second transistor, and outputs a reference voltage from the otherend of said fourth electric current path to one end of said fourthelectric current path, a first value indicative of a channel-width/achannel-length of said fourth transistor being equal to or larger than asecond value indicative of a channel-width/a channel-length of saidsecond transistor.
 2. The shift register according to claim 1, furthercomprising a fifth transistor having a fifth control terminal whichresets a voltage applied to said wiring between said second controlterminal of said second transistor and the other end of said firstelectric current path of said first transistor by turning on said fifthcontrol terminal by an output signal of the other stage.
 3. A shiftregister comprising a plurality of stages electrically connected to eachother, each of said stages comprising: a first transistor having a firstcontrol terminal, which is turned on by a signal on a predeterminedlevel supplied from one stage to said first control terminal, andoutputs said signal on a predetermined level from one end of a firstelectric current path to the other end of said first electric currentpath; a second transistor having a second control terminal, which isturned on in accordance with a voltage applied to a wiring between saidsecond control terminal and the other end of said first electric currentpath of said first transistor, and outputs a first or second signalsupplied from outside to one end of a second electric current path as anoutput signal from the other end of said second electric current path; athird transistor having a third control terminal, which outputs a powersupply voltage from one end of a third electric current path to theother end of said third electric current path; a fourth transistorhaving a fourth control terminal, which is turned on in accordance witha voltage applied to a wiring between said fourth control terminal andthe other end of said first electric current path of said firsttransistor, and outputs from one end of a fourth electric current pathto the other end of said fourth electric current path said power supplyvoltage supplied from said third transistor so that said power supplyvoltage outputted from said third transistor is displaced to a voltageon a predetermined level; and a fifth transistor having a fifth controlterminal, which is turned on in accordance with a voltage applied to awiring between said fifth control terminal and said third transistor,has one end of a fifth electric current path being connected to theother end of said second electric current path of said secondtransistor, and outputs a reference voltage from the other end of saidfifth electric current path to one end of said fifth electric currentpath, a first value indicative of a channel-width/a channel-length ofsaid third transistor being larger than 1/20 of a second valueindicative of a channel-width/a channel-length of said secondtransistor.
 4. The shift register according to claim 3, furthercomprising a sixth transistor having a sixth control terminal, whichresets a voltage applied to said wiring between said second controlterminal of said second transistor and the other end of said firstelectric current path of said first transistor by turning on said sixthcontrol terminal by an output signal of the other stage.
 5. A shiftregister comprising a plurality of stages electrically connected to eachother, each of said stages comprising: a first transistor having a firstcontrol terminal, which is turned on by a signal on a predeterminedlevel supplied from one stage to said first control terminal, andoutputs said signal on a predetermined level from one end of a firstelectric current path to the other end of said first electric currentpath; a second transistor having a second control terminal, which isturned on in accordance with a voltage applied to a wiring between saidsecond control terminal and the other end of said first electric currentpath of said first transistor, and outputs a first or second signalsupplied from outside to one end of a second electric current path as anoutput signal from the other end of said second electric current path; athird transistor having a third control terminal, which outputs a powersupply voltage from one end of a third electric current path to theother end of said third electric current path; a fourth transistorhaving a fourth control terminal, which is turned on in accordance witha voltage applied to a wiring between said fourth control terminal andthe other end of said first electric current path of said firsttransistor, and outputs from one end of a fourth electric current pathto the other end of said fourth electric current path said power supplyvoltage supplied from said third transistor so that said power supplyvoltage outputted from said third transistor is displaced to a voltageon a predetermined level; a fifth transistor having a fifth controlterminal, which is turned on in accordance with a voltage applied to awiring between said fifth control terminal and said third transistor,has one end of a fifth electric current path being connected to theother end of said second electric current path of said secondtransistor, and outputs a reference voltage from the other end of saidfifth electric current path to one end of said fifth electric currentpath; and a sixth transistor having a sixth control terminal, whichresets a voltage applied to said wiring between said second controlterminal of said second transistor and the other end of said firstelectric current path of said first transistor by turning on said sixthcontrol terminal by an output signal of the other stage, a first valueindicative of a channel-width/a channel-length of said fifth transistorbeing larger than a second value indicative of a channel-width/achannel-length of said first transistor.
 6. The shift register accordingto claim 5, wherein a third value indicative of a channel-width/achannel-length of said second transistor is larger than said secondvalue.
 7. The shift register according to claim 5, wherein said firstvalue is larger than a fourth value indicative of a channel-width/achannel-length of said sixth transistor.
 8. The shift register accordingto claim 5, wherein a third value indicative of a channel-width/achannel-length of said second transistor is larger than a fourth valueindicative of a channel-width/a channel-length of said sixth transistor.9. The shift register according to claim 5, wherein said second value islarger than a fifth value indicative of a channel-width/a channel-lengthof said third transistor.
 10. The shift register according to claim 5,wherein a fourth value indicative of a channel-width/a channel-length ofsaid sixth transistor is larger than a fifth value indicative of achannel-width/a channel-length of said third transistor.
 11. The shiftregister according to claim 5, wherein said second value is larger thana sixth value indicative of a channel-width/a channel-length of saidfourth transistor.
 12. The shift register according to claim 5, whereina fourth value indicative of a channel-width/a channel-length of saidsixth transistor is larger than a sixth value indicative of achannel-width/a channel-length of said fourth transistor.
 13. A shiftregister comprising a plurality of stages electrically connected to eachother, each stage of said shift register comprising: a first transistorhaving a first control terminal to which an output signal of a stage onone side is supplied and one end of an electric current path to which afirst voltage signal is supplied; a second transistor having a secondcontrol terminal to which an output signal of a stage on the other sideis supplied and one end of an electric current path to which a secondvoltage signal is supplied; and a third transistor having a thirdcontrol terminal being connected to the other end of each electriccurrent path of said first and second transistors, which is turned on oroff by said first or second voltage signal supplied to a wiring betweensaid third control terminal and said first or second transistor throughsaid first or second transistor, and outputs as an output signal of thecorresponding stage from the other end of an electric current path afirst or second clock signal supplied to one end of said electriccurrent path when turned on, at least one of said first and secondtransistors discharging electric charge accumulated in said wiring by anoutput signal of a stage on one side or the other side supplied to saidfirst or second control terminal.
 14. The shift register according toclaim 13, wherein one of said first and second transistors of a stage onone end in a plurality of said stages is turned on when a first controlsignal is supplied from outside to said control terminal, and electriccharge is thereby accumulated in said wiring; and the other one of saidfirst and second transistors of a stage on the other end in a pluralityof said stages is turned on when a second control signal is suppliedfrom outside to said control terminal, and electric charge accumulatedin said wiring is thereby discharged.
 15. The shift register accordingto claim 13, wherein by switching levels of said first and secondvoltage signals, electric charge is accumulated in said wiring throughone of said first and second transistors, and electric chargeaccumulated in said wiring can be discharged through the other one ofsaid first and second transistors.
 16. The shift register according toclaim 15, wherein levels of said first and second voltage signals areswitched in such a manner than one of said first and second voltagesignals is maintained on a low level.
 17. The shift register accordingto claim 13, wherein a phase of said first clock signal and that of saidsecond clock signal are different from each other by 180°.
 18. The shiftregister according to claim 13, wherein respective transistorsconstituting each stage of a plurality of said stages are field effecttransistors which are of the same channel type.
 19. The shift registeraccording to claim 13, further comprising: a fourth transistor having afourth control terminal connected to the other end of each electriccurrent path of said first and second transistors, which has on and offtimings synchronized with said third transistor, and discharges from theother end of an electric current path a signal supplied from a voltagesource to one end of said electric current path through a load whenturned on; and a fifth transistor having a fifth control terminalconnected to said voltage source through said load, which is turned onby a signal connected from said voltage source when said fourthtransistor is turned off, and has one end of an electric current pathconnected to the other end of an electric current path of said thirdtransistor.
 20. An electronic apparatus comprising: (A) a shift registercomprising in each stage: a first transistor having a first controlterminal, which is turned on by a signal on a predetermined levelsupplied from one stage to said first control terminal, and outputs saidsignal on a predetermined level from one end of a first electric currentpath to the other end of said first electric current path; a secondtransistor having a second control terminal, which is turned on inaccordance with a voltage applied to a wiring between said secondcontrol terminal and the other end of said first electric current pathof said first transistor, and outputs a first or second signal suppliedfrom outside to one end of a second electric current path as an outputsignal from the other end of said second electric current path; a thirdtransistor having a third control terminal, which outputs a power supplyvoltage from one end of a third electric current path to the other endof said third electric current path; a fourth transistor having a fourthcontrol terminal, which is turned on in accordance with a voltageapplied to a wiring between said fourth control terminal and the otherend of said first electric current path of said first transistor, andoutputs from one end of a fourth electric current path to the other endof said fourth electric current path said power supply voltage suppliedfrom said third transistor so that said power supply voltage outputtedfrom said third transistor is displaced to a voltage on a predeterminedlevel; a fifth transistor having a fifth control terminal, which isturned on in accordance with a voltage applied to a wiring between saidfifth control terminal and said third transistor, has one end of a fifthelectric current path being connected to the other end of said secondelectric current path of said second transistor, and outputs a referencevoltage from the other end of said fifth electric current path to oneend of said fifth electric current path; and a sixth transistor having asixth control terminal, which resets a voltage applied to said wiringbetween said second control terminal of said second transistor and theother end of said first electric current path of said first transistorby turning on said sixth control terminal by an output signal of theother stage; and (B) a drive device driven in accordance with saidoutput signals from said second transistors of said shift register, afirst value indicative of a channel-width/a channel-length of said fifthtransistor being larger than a second value indicative of achannel-width/a channel-length of said first transistor.
 21. Theelectronic apparatus according to claim 20, wherein a third valueindicative of a channel-width/a channel-length of said second transistoris larger than said second value.
 22. The electronic apparatus accordingto claim 20, wherein said first value is larger than a fourth valueindicative of a channel-width/a channel-length of said sixth transistor.23. The electronic apparatus according to claim 20, wherein a thirdvalue indicative of a channel-width/a channel-length of said secondtransistor is larger than a fourth value of a channel-width/achannel-length of said sixth transistor.
 24. The electronic apparatusaccording to claim 20, wherein said second value is larger than a fifthvalue indicative of a channel-width/a channel-length of said thirdtransistor.
 25. The electronic apparatus according to claim 20, whereina fourth value indicative of a channel-width/a channel-length of saidsixth transistor is larger than a fifth value indicative of achannel-width/a channel-length of said third transistor.
 26. Theelectronic apparatus according to claim 20, wherein said second value islarger than a sixth value indicative of a channel-width/a channel-lengthof said fourth transistor.
 27. The electronic apparatus according toclaim 20, wherein a fourth value indicative of a channel-width/achannel-length of said sixth transistor is larger than a sixth valueindicative of a channel-width/a channel-length of said fourthtransistor.
 28. The electronic apparatus according to claim 20, whereinsaid drive device includes a liquid crystal display device.
 29. Theelectronic apparatus according to claim 20, wherein said drive devicehas a photosensor.
 30. A shift register comprising a plurality of stageselectrically connected to each other, at least one of said stagescomprising: a first transistor having a first control terminal, which isturned on by a signal on a predetermined level supplied from one stageto said first control terminal, and outputs a signal on a predeterminedlevel from one end of a first electric current path to the other end ofsaid first electric current path; a second transistor having a secondcontrol terminal, which is turned on in accordance with a voltageapplied to a wiring between said second control terminal and the otherend of said first electric current path of said first transistor, andoutputs a signal supplied from outside to one end of a second electriccurrent path as an output signal from the other end of said secondelectric current path; a load for outputting a power supply voltagesupplied from outside; a third transistor having a third controlterminal, which is turned on in accordance with a voltage applied to awiring between said third control terminal and the other end of saidfirst electric current path of said first transistor, and outputs saidpower supply voltage, which is fed from outside through said load, fromone end of a third electric current path to the other end of said thirdelectric current path so that said power supply voltage outputted fromsaid load is displaced to a voltage on a predetermined level; and afourth transistor having a fourth control terminal, which is turned onin accordance with a voltage applied to a wiring between said fourthcontrol terminal and said load, has one end of a fourth electric currentpath, connected to the other end of said second electric current path ofsaid second transistor, and outputs a reference voltage from the otherend of said fourth electric current path to one end of said fourthelectric current path; wherein a first value indicative of achannel-width/a channel-length of said fourth transistor is equal to orlarger than a second value indicative of a channel-width/achannel-length of said second transistor.
 31. An electronic apparatuscomprising: (A) a shift register comprising a plurality of stageselectrically connected to each other, at least one of said stagesincluding: a first transistor having a first control terminal, which isturned on by a signal on a predetermined level supplied from one stageto said first control terminal, and outputs a signal on a predeterminedlevel from one end of a first electric current path to the other end ofsaid first electric current path; a second transistor having a secondcontrol terminal, which is turned on in accordance with a voltageapplied to a wiring between said second control terminal and the otherend of said first electric current path of said first transistor, andoutputs a signal supplied from outside to one end of a second electriccurrent path as an output signal from the other end of said secondelectric current path; a load for outputting a power supply voltagesupplied from outside; a third transistor having a third controlterminal, which is turned on in accordance with a voltage applied to awiring between said third control terminal and the other end of saidfirst electric current path of said first transistor, and outputs saidpower supply voltage, which is fed from outside through said load, fromone end of a third electric current path to the other end of said thirdelectric current path so that said power supply voltage outputted fromsaid load is displaced to a voltage on a predetermined level; and afourth transistor having a fourth control terminal, which is turned onin accordance with a voltage applied to a wiring between said fourthcontrol terminal and said load, has one end of a fourth electric currentpath, connected to the other end of said second electric current path ofsaid second transistor, and outputs a reference voltage from the otherend of said fourth electric current path to one end of said fourthelectric current path; and (B) a drive device driven in accordance withsaid output signal from said at least one second transistor of saidshift register; wherein a first value indicative of a channel-width/achannel-length of said fourth transistor is equal to or larger than asecond value indicative of a channel-width/a channel-length of saidsecond transistor.
 32. A shift register comprising a plurality of stageselectrically connected to each other, at least one of said stagescomprising: a first transistor having a first control terminal, which isturned on by a signal on a predetermined level supplied from one stageto said first control terminal, and outputs a signal on a predeterminedlevel from one end of a first electric current path to the other end ofsaid first electric current path; a second transistor having a secondcontrol terminal, which is turned on in accordance with a voltageapplied to a wiring between said second control terminal and the otherend of said first electric current path of said first transistor, andoutputs a signal supplied from outside to one end of a second electriccurrent path as an output signal from the other end of said secondelectric current path; a third transistor having a third controlterminal, which outputs a power supply voltage from one end of a thirdelectric current path to the other end of said third electric currentpath; a fourth transistor having a fourth control terminal, which isturned on in accordance with a voltage applied to a wiring between saidfourth control terminal and the other end of said first electric currentpath of said first transistor, and outputs from one end of a fourthelectric current path to the other end of said fourth electric currentpath said power supply voltage supplied from said third transistor sothat said power supply voltage outputted from said third transistor isdisplaced to a voltage on a predetermined level; and a fifth transistorhaving a fifth control terminal, which is turned on in accordance with avoltage applied to a wiring between said fifth control terminal and saidthird transistor, has one end of a fifth electric current path beingconnected to the other end of said second electric current path of saidsecond transistor, and outputs a reference voltage from the other end ofsaid fifth electric current path to one end of said fifth electriccurrent path; wherein a first value indicative of a channel-width/achannel-length of said third transistor is larger than 1/20 of a secondvalue indicative of a channel-width/a channel-length of said secondtransistor.
 33. An electronic apparatus comprising: (A) a shift registercomprising a plurality of stages electrically connected to each other,at least one of said stages including: a first transistor having a firstcontrol terminal, which is turned on by a signal on a predeterminedlevel supplied from one stage to said first control terminal, andoutputs a signal on a predetermined level from one end of a firstelectric current path to the other end of said first electric currentpath; a second transistor having a third control terminal, which isturned on in accordance with a voltage applied to a wiring between saidsecond control terminal and the other end of said first electric currentpath of said first transistor, and outputs a signal supplied fromoutside to one end of a second electric current path as an output signalfrom the other end of said second electric current path; a thirdtransistor having a third control terminal, which outputs a power supplyvoltage from one end of a third electric current path to the other endof said third electric current path; a fourth transistor having a fourthcontrol terminal, which is turned on in accordance with a voltageapplied to a wiring between said fourth control terminal and the otherend of said first electric current path of said first transistor, andoutputs from one end of a fourth electric current path to the other endof said fourth electric current path said power supply voltage suppliedfrom said third transistor so that said power supply voltage outputtedfrom said third transistor is displaced to a voltage on a predeterminedlevel; and a fifth transistor having a fifth control terminal, which isturned on in accordance with a voltage applied to a wiring between saidfifth control terminal and said third transistor, has one end of a fifthelectric current path being connected to the other end of said secondelectric current path of said second transistor, and outputs a referencevoltage from the other end of said fifth electric current path to oneend of said fifth electric current path; and (B) a drive device drivenin accordance with said output signal from said at least one secondtransistor of said shift register; wherein a first value indicative of achannel-width/a channel-length of said third transistor is larger then1/20 of a second value indicative of a channel-width/a channel-length ofsaid second transistor.
 34. A shift register comprising a plurality ofstages electrically connected to each other, at least one of said stagescomprising: a first transistor having a first control terminal, which isturned on by a signal on a predetermined level supplied from one stageto said first control terminal, and outputs a signal on a predeterminedlevel from one end of a first electric current path to the other end ofsaid first electric current path; a second transistor having a secondcontrol terminal, which is turned on in accordance with a voltageapplied to a wiring between said second control terminal and the otherend of said first electric current path of said first transistor, andoutputs a signal supplied from outside to one end of a second electriccurrent path as an output signal from the other end of said secondelectric current path; a third transistor having a third controlterminal, which outputs a power supply voltage from one end of a thirdelectric current path to the other end of said third electric currentpath; a fourth transistor having a fourth control terminal, which isturned on in accordance with a voltage applied to a wiring between saidfourth control terminal and the other end of said first electric currentpath of said first transistor, and outputs from one end of a fourthelectric current path to the other end of said fourth electric currentpath said power supply voltage supplied from said third transistor sothat said power supply voltage outputted from said third transistor isdisplaced to a voltage on a predetermined level; a fifth transistorhaving a fifth control terminal, which is turned on in accordance with avoltage applied to a wiring between said fifth control terminal and saidthird transistor, has one end of a fifth electric current path beingconnected to the other end of said second electric current path of saidsecond transistor, and outputs a reference voltage from the other end ofsaid fifth electric current path to one end of said fifth electriccurrent path; and a sixth transistor having a sixth control terminal,which resets a voltage applied to said wiring between said secondcontrol terminal of said second transistor and the other end of saidfirst electric current path of said first transistor by turning on saidsixth control terminal by an output signal of the other stage; wherein afirst value indicative of a channel-width/a channel-length of said fifthtransistor is larger than a second value indicative of a channel-width/achannel-length of said first transistor.
 35. An electronic apparatuscomprising: (A) a shift register comprising a plurality of stageselectrically connected to each other, at least one of said stagesincluding: a first transistor having a first control terminal, which isturned on by a signal on a predetermined level supplied from one stageto said first control terminal, and outputs a signal on a predeterminedlevel from one end of a first electric current path to the other end ofsaid first electric current path; a second transistor having a secondcontrol terminal, which is turned on in accordance with a voltageapplied to a wiring between said second control terminal and the otherend of said first electric current path of said first transistor, andoutputs a signal supplied from outside to one end of a second electriccurrent path as an output signal from the other end of said secondelectric current path; a third transistor having a third controlterminal, which outputs a power supply voltage from one end of a thirdelectric current path to the other end of said third electric currentpath; a fourth transistor having a fourth control terminal, which isturned on in accordance with a voltage applied to a wiring between saidfourth control terminal and the other end of said first electric currentpath of said first transistor, and outputs from one end of a fourthelectric current path to the other end of said fourth electric currentpath said power supply voltage supplied from said third transistor sothat said power supply voltage outputted from said third transistor isdisplaced to a voltage on a predetermined level; a fifth transistorhaving a fifth control terminal, which is turned on in accordance with avoltage applied to a wiring between said fifth control terminal and saidthird transistor, has one end of a fifth electric current path beingconnected to the other end of said second electric current path of saidsecond transistor, and outputs a reference voltage from the other end ofsaid fifth electric current path to one end of said fifth electriccurrent path; and a sixth transistor having a sixth control terminal,which resets a voltage applied to said wiring between said secondcontrol terminal of said second transistor and the other end of saidfirst electric current path of said first transistor by turning on saidsixth control terminal by an output signal of the other stage; and (B) adrive device driven in accordance with said output signal from said atleast one second transistor of said shift register; wherein a firstvalue indicative of a channel-width/a channel-length of said fifthtransistor is larger than a second value indicative of a channel-width/achannel-length of said first transistor.
 36. A shift register comprisinga plurality of stages electrically connected to each other, at least oneof said stages comprising: a first transistor having a first controlterminal to which a signal of a stage on one side is supplied and oneend of an electric current path to which a first voltage signaldiffering from said signal is supplied; a second transistor having asecond control terminal to which a signal of a stage on the other sideis supplied and one end of an electric current path to which a secondvoltage signal is supplied; and a third transistor having a thirdcontrol terminal being connected to the other end of each electriccurrent path of said first and second transistors, which is turned on oroff by said first or second voltage signal supplied to a wiring betweensaid third control terminal and said first or second transistor throughsaid first or second transistor, and outputs as an output signal of thecorresponding stage from the other end of an electric current path aclock signal supplied to one end of said electric current path whenturned on; wherein at least one of said first and second transistorsdischarges electric charges accumulated in said wiring by a signal of astage on one side or the other side supplied to said first or secondcontrol terminal.
 37. An electronic apparatus comprising: (A) a shiftregister comprising a plurality of stages electrically connected to eachother, at least one of said stages including: a first transistor havinga first control terminal to which a signal of a stage on one side issupplied and one end of an electric current path to which a firstvoltage signal differing from said signal is supplied; a secondtransistor having a second control terminal to which a signal of a stageon the other side is supplied and one end of an electric current path towhich a second voltage signal is supplied; and a third transistor havinga third control terminal being connected to the other end of eachelectric current path of said first and second transistors, which isturned on or off by said first or second voltage signal supplied to awiring between said third control terminal and said first or secondtransistor through said first or second transistor, and outputs as anoutput signal of the corresponding stage from the other end of anelectric current path a clock signal supplied to one end of saidelectric current path when turned on; wherein at least one of said firstand second transistors discharges electric charges accumulated in saidwiring by a signal of a stage on one side or the other side supplied tosaid first or second control terminal; and (B) a drive device driven inaccordance with said output signal from said at least one thirdtransistor of said shift register.
 38. A shift register comprising aplurality of stages electrically connected to each other, at least oneof said stages comprising: a first transistor having a first controlterminal to which a signal of a preceding stage is supplied and one endof a first electric current path to which a first voltage signaldiffering from said signal is supplied; a second transistor having asecond control terminal to which a signal of a next stage is suppliedand one end of a second electric current path to which a second voltagesignal is supplied; and a third transistor having a third controlterminal being connected to the other end of each of the first andsecond electric current paths of said first and second transistors,which is turned on or off by said first or second voltage signalsupplied to a wiring between said third control terminal and said firstor second transistor through said first or second transistor, andoutputs as an output signal of the corresponding stage from the otherend of a third electric current path a clock signal supplied to one endof said electric current path when turned on; wherein at least one ofsaid first and second transistors discharges electric chargesaccumulated in said wiring by a signal of said preceding stage or saidnext stage supplied to said first or second control terminal.
 39. Anelectronic apparatus comprising: (A) a shift register comprising aplurality of stages electrically connected to each other, at least oneof said stages including: a first transistor having a first controlterminal to which a signal of a preceding stage is supplied and one endof a first electric current path to which a first voltage signaldiffering from said signal is supplied; a second transistor having asecond control terminal to which a signal of a next stage is suppliedand one end of a second electric current path to which a second voltagesignal is supplied; and a third transistor having a third controlterminal being connected to the other end of each of the first andsecond electric current paths of said first and second transistors,which is turned on or off by said first or second voltage signalsupplied to a wiring between said third control terminal and said firstor second transistor through said first or second transistor, andoutputs as an output signal of the corresponding stage from the otherend of a third electric current path a clock signal supplied to one endof said electric current path when turned on; wherein at least one ofsaid first and second transistors discharges electric chargesaccumulated in said wiring by a signal of said preceding stage or saidnext stage supplied to said first or second control terminal; and (B) adrive device driven in accordance with said output signal from said atleast one third transistor of said shift register.
 40. A shift registercomprising a plurality of stages electrically connected to each other,at least one of said stages comprising: a first transistor having afirst control terminal to which a signal of a preceding stage issupplied and one end of a first electric current path to which a firstvoltage signal differing from said signal is supplied; a secondtransistor having a second control terminal to which a signal of a nextstage is supplied an one end of a second electric current path to whicha second voltage signal is supplied; a third transistor having a thirdcontrol terminal being connected to the other end of each of the firstand second electric current paths of said first and second transistors,which is turned on or off by said first or second voltage signalsupplied to a wiring between said third control terminal and said firstor second transistor through said first or second transistor, andoutputs as an output signal of the corresponding stage from the otherend of a third electric current path a clock signal supplied to one endof said third electric current path when turned on; a fourth transistorhaving a fourth control terminal, which outputs a power supply voltagefrom one end of a fourth electric current path to the other end of saidfourth electric current path; a fifth transistor having a fifth controlterminal, which is turned on in accordance with a voltage applied to awiring between said fifth control terminal and the other end of saidfirst electric current path of said first transistor, and outputs fromone end of a fifth electric current path to the other end of said fifthelectric current path said power supply voltage supplied from saidfourth transistor so that said power supply voltage outputted from saidfourth transistor is displaced to a voltage on a predetermined level;and a sixth transistor having a sixth control terminal, which is turnedon in accordance with a voltage applied to a wiring between said sixthcontrol terminal and said fourth transistor, has one end of a sixthelectric current path being connected to the other end of said thirdelectric current path of said third transistor, and outputs a referencevoltage from the other end of said sixth electric current path to oneend of said sixth electric current path; wherein at least one of saidfirst and second transistors discharges electric charges accumulated insaid wiring by a signal of said preceding stage or said next stagesupplied to said first or second control terminal.
 41. An electronicapparatus comprising: (A) a shift register comprising a plurality ofstages electrically connected to each other, at least one of said stagesincluding: a first transistor having a first control terminal to which asignal of a preceding stage is supplied and one end of a first electriccurrent path to which a first voltage signal differing from said signalis supplied; a second transistor having a second control terminal towhich a signal of a next stage is supplied and one end of a secondelectric current path to which a second voltage signal is supplied; athird transistor having a third control terminal being connected to theother end of each of the first and second electric current paths of saidfirst and second transistors, which is turned on or off by said first orsecond voltage signal supplied to a wiring between said third controlterminal and said first or second transistor through said first orsecond transistor, and outputs as an output signal of the correspondingstage from the other end of a third electric current path a clock signalsupplied to one end of said third electric current path when turned on;a fourth transistor having a fourth control terminal, which outputs apower supply voltage from one end of a fourth electric current path tothe other end of said fourth electric current path; a fifth transistorhaving a fifth control terminal, which is turned on in accordance with avoltage applied to a wiring between said fifth control terminal and theother end of said first electric current path of said first transistor,and outputs from one end of a fifth electric current path to the otherend of said fifth electric current path said power supply voltagesupplied from said fourth transistor so that said power supply voltageoutputted from said fourth transistor is displaced to a voltage on apredetermined level; and a sixth transistor having a sixth controlterminal, which is turned on in accordance with a voltage applied to awiring between said sixth control terminal and said fourth transistor,has one end of a sixth electric current path being connected to theother end of said third electric current path of said third transistor,and outputs a reference voltage from the other end of said sixthelectric current path to one end of said sixth electric current path;wherein at least one of said first and second transistors dischargeselectric charges accumulated in said wiring by a signal of saidpreceding stage or said next stage supplied to said first or secondcontrol terminal; and (B) a drive device driven in accordance with saidoutput signal from said at least one third transistor of said shiftregister.